Computing-in-Memory Voltage Feedback for Linear Low-Power Output
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Solution Overview
Problem
Conventional computing-in-memory architectures face issues with excessive power consumption and non-linear output current due to voltage offset and parasitic capacitance, affecting the linearity and efficiency of computing operations.
Innovation Solution
A computing-in-memory apparatus combining a SRAM array with a distributed voltage regulator and a detection circuit, utilizing sub-threshold automatic bias design and negative feedback mechanisms to adjust operation voltage and reduce power consumption, thereby normalizing output current and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current mode is used for multiply accumulate operations, then parallelization is achieved, but output current cannot be effectively controlled resulting in excessive power consumption
Solution Approach 1:
The patent implements a feedback mechanism where the output current from bitline accumulation is fed back to adjust the wordline drive voltage. This feedback loop dynamically controls the output current to prevent excessive current draw while maintaining parallelization benefits, directly resolving the contradiction between productivity and power consumption.
Solution Approach 2:
The patent changes the operating parameters by introducing adaptive wordline voltage control based on detected output current levels. By dynamically adjusting the wordline drive voltage parameter in response to current conditions, the system maintains efficient parallel operations while preventing excessive power consumption.
2Use of energy by moving object
If wordline drive voltage is reduced for small current output, then power consumption decreases, but switching elements enter sub-threshold region causing non-linear output
Solution Approach 1:
The detection circuit monitors output current and provides feedback to adjust wordline voltage dynamically. This ensures the switching elements remain in the optimal operating region (above sub-threshold) while minimizing power consumption, thereby maintaining linearity without excessive power draw.
Solution Approach 2:
The patent introduces dynamic wordline voltage adjustment rather than static voltage levels. The wordline drive voltage adapts in real-time based on operating conditions, allowing the system to maintain linear operation when needed while reducing power consumption during low-activity periods.
3Area of stationary object
If unit capacitance is reduced to 1 fF to save area, then area usage efficiency improves, but parasitic capacitance affects charge redistribution causing non-linear output
Solution Approach 1:
The patent applies preliminary compensation for parasitic capacitance effects through the feedback mechanism. By detecting output deviations caused by parasitic capacitance and adjusting wordline voltage in advance, the system counteracts the non-linear effects before they significantly impact output linearity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption, normalizes output current, and enhances linearity by automatically adjusting operation voltage based on accurate reference currents, addressing manufacturing and temperature variations in computing units.
Implementation Method 1
a negative feedback convergence or a negative feedback mechanism is performed according to a comparison result of the output current of the detection circuit and the reference current source of the voltage regulator
Data Source
AI summary
A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.