Compute-in-Memory Weighted Summation With Stable Bit Line Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional compute-in-memory circuits suffer from non-linear computation results due to unstable bit line voltages, affecting system performance and energy efficiency.
Innovation Solution
A weighted summation compute-in-memory circuit is introduced, utilizing two symmetric arrays and peripheral circuits to perform bitwise array vector multiplication and analog summation, stabilizing voltage through parasitic capacitors and reducing the need for additional capacitors, thereby improving energy and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional compute-in-memory circuits are used with small bit line parasitic capacitors, then the area is reduced, but the voltage on the bit line becomes unstable and computation results become nonlinear
Solution Approach 1:
The patent merges the functions of the first array (bitwise array vector multiplication) and the second array (analog summation with weighted summation) into a unified compute-in-memory system. The second array is configured to provide parasitic capacitance that stabilizes the bit line voltage during computation, eliminating the need for separate stabilization capacitors while maintaining nonlinear computation accuracy.
Solution Approach 2:
The second array serves multiple functions: it performs analog summation of computation results, provides parasitic capacitance for voltage stabilization, and enables weighted summation operations. This multi-functionality reduces the need for additional dedicated components while improving system efficiency.
2Stability of the object's composition
If additional capacitors are added to stabilize bit line voltage, then voltage stability improves, but the area and device complexity increase
Solution Approach 1:
The patent combines the voltage stabilization function into the existing second array structure, eliminating the need for separate stabilization capacitors. The second array's inherent parasitic capacitance is utilized to stabilize bit line voltage, reducing component count and system complexity.
Solution Approach 2:
The second array provides its own parasitic capacitance to stabilize the bit line voltage, making the system self-sufficient. No external stabilization components are needed as the system uses its own internal resources (the second array's capacitance) to achieve voltage stability.
3Measurement precision
If the analog-to-digital converter operates multiple times to handle increased computation parallelism, then computation accuracy is maintained, but the number of converter startups increases and energy efficiency decreases
Solution Approach 1:
The patent enables continuous computation and readout operations by maintaining stable bit line voltage throughout the computation process. The weighted summation circuit allows for continuous analog summation without requiring multiple discrete ADC operations, reducing the number of converter startups and improving energy efficiency.
4Ease of operation
If DC process is used in compute-in-memory circuit, then the circuit operation is simplified, but larger current flows through the array and operational amplifier reducing energy efficiency
Solution Approach 1:
The patent employs pulsed operation modes where the compute-in-memory circuit operates in periodic cycles rather than continuous DC operation. This allows for controlled current flow during computation phases while maintaining operational simplicity, improving energy efficiency by eliminating continuous current consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes computation voltages, reduces the number of analog-to-digital converter startups, and enhances system efficiency by eliminating the need for additional capacitors, while maintaining parallelism.
Implementation Method 1
Based on Ohm's law and Kirchhoff's law computation in the array, a current is obtained at the other end of the array
Implementation Method 2
Based on Ohm's law and Kirchhoff's law computation in the array
Implementation Method 3
weight values are stored in a non-volatile memory cell, and analog vector matrix multiplication computation is performed in an array
Implementation Method 4
stabilizing voltage through parasitic capacitors
Implementation Method 5
The quantity of charge lost on the BL parasitic capacitor is equal to the sum of the quantities of charge flowing through the devices
Data Source
AI summary
The present disclosure provides a weighted summation compute-in-memory circuit and a memory, the circuit includes: a first array and a second array symmetrically distributed, and a peripheral circuit; when the first array is use for compute-in-memory, the first array is disconnected from the second array through the peripheral circuit, and the first array performs a bitwise array vector multiplication operation; then the first array is connected to the second array through the peripheral circuit, the first array and the second array form a switched-capacitor circuit, the second array performs an analog summation and an analog weighted summation operation corresponding to the pulse signal, and output an operation result.