Compute-in-Memory Wordline Control for Low-Power DNN Multiplication
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Solution Overview
Problem
Existing memory devices struggle to perform fast computations required by deep neural networks (DNNs) due to limitations in bandwidth and power consumption, necessitating a new structure for memory cells that can efficiently perform multiplications and additions between activation values and weights.
Innovation Solution
A memory device with a wordline decoder and shift adder system that controls wordlines based on weight values, allowing for efficient multiplication and addition operations while reducing power consumption, utilizing a memory cell array that stores activation values in a novel configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional memory cell structure is used, then manufacturing is simple, but power consumption is high and computational efficiency is low
Solution Approach 1:
The memory cell array is divided into multiple banks (first bank, second bank, third bank, fourth bank) with different wordline configurations. Each bank can be independently controlled, allowing selective activation of only the memory cells needed for computation, thereby reducing overall power consumption while managing structural complexity through modular organization.
Solution Approach 2:
The system dynamically selects and activates specific wordlines based on computational requirements. The wordline decoder activates only the necessary wordlines for the current computation task, enabling adaptive power management where power consumption varies according to the computational workload rather than remaining static.
2Speed
If memory bandwidth is increased to meet computational requirements, then processing speed improves, but power consumption increases
Solution Approach 1:
The system performs partial computations within the memory device by implementing compute-in-memory functionality. Instead of transferring all data for processing, the memory device performs partial multiplication and accumulation operations directly on stored data, achieving computational speedup while using only the power necessary for selective computation rather than full data transfer and processing.
Solution Approach 2:
The wordline decoder acts as an intermediary that selectively activates memory cells based on computational needs. It mediates between the computational requirements and the memory cell array, enabling efficient computation by activating only the necessary memory cells and their associated read circuits, thereby achieving high computational speed with reduced power consumption.
3Productivity
If activation values are stored in conventional configuration, then storage is simple, but multiplication operations are slow
Solution Approach 1:
Different banks of the memory cell array use different wordline configurations optimized for specific computational patterns. For example, some banks may have wordlines optimized for row-wise operations while others are optimized for column-wise operations, allowing multiplication operations to be performed efficiently in parallel across different banks with locally optimized storage configurations.
Solution Approach 2:
The system utilizes multiple dimensions of the memory array (different banks, different wordlines, different bitlines) to perform parallel multiplication operations. By organizing activation values across multiple spatial dimensions and enabling simultaneous access through the bank structure, the system achieves high multiplication throughput without requiring a fundamentally complex storage configuration within each bank.
Data Source
AI summary
A memory device including a wordline decoder that controls a plurality of wordlines and selects a wordline, to which a first turn-on voltage is applied, depending on a weight value to be applied to an activation value, a first memory cell array that includes memory cells respectively connected to wordlines, and a shift adder that is connected to the first memory cell array through a first bitline and a first bitline bar and generates a first initial calculation result by adding a first input received through the first bitline and a second input received through the first bitline bar. The first memory cell array stores a first activation value including a first bit and a second bit. The first bit is stored in a first memory cell connected to the first wordline. The second bit is stored in a second memory cell connected to the second wordline.