Compute-in-Memory Zero Skipping for Sparse Operand Power Savings

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Solution Overview

Problem

Conventional compute-in-memory circuits are inefficient due to energy consumption during computations where one or more operands are zero, as they do not compensate for zero input data, leading to unnecessary power consumption.

Innovation Solution

Implementing a zero-detection circuit in CIM circuits to detect when at least one operand is zero, disabling components such as memory access, multiplication, and mantissa shift operations, thereby reducing power consumption while preserving computational accuracy and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional compute-in-memory circuits perform computations without zero detection, then computational throughput is maintained, but power consumption increases due to unnecessary operations on zero operands

Engineering Contradiction:
Improvepower consumptionVSAvoidcomputational throughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The zero-detection circuit performs preliminary detection of zero operands before the main computation operations (memory access, multiplication, mantissa shift) are executed. By detecting zeros in advance, the system can disable subsequent energy-consuming operations, thereby reducing power consumption without significantly impacting computational throughput since the detection overhead is minimal compared to the full computation pipeline.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If zero-detection circuit is implemented to disable components, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The zero-detection circuit acts as an intermediary component between the input data and the main computation units (memory array, multiplier, mantissa shift circuit). This intermediary detects zero conditions and generates control signals that enable or disable the downstream computation components, thereby reducing power consumption while adding only a single-layer overhead to the existing circuit architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If conventional circuits process all operands uniformly, then computational accuracy is maintained, but energy efficiency deteriorates due to processing zero operands

Engineering Contradiction:
Improveenergy efficiencyVSAvoidcomputational accuracy
Core Design Contradiction:
Loss of energyVSMeasurement precision

Solution Approach 1:

The system applies different processing quality to different operands by detecting zero values and applying a specialized processing path (disabling computation) only to those specific cases. Non-zero operands continue to undergo full computation operations. This local differentiation maintains computational accuracy for all operands while significantly improving energy efficiency by avoiding unnecessary operations on zero operands.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250362870A1Sparsity-aware zero skipping for compute-in-memory circuits
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250362870A1 patent drawing
  • US20250362870A1 patent drawing
  • US20250362870A1 patent drawing

AI summary

A system, circuit, and method of operation of the system and circuit are disclosed. In one aspect, a device includes a computation circuit, a memory array, and a controller. The controller can determine that one or more input data bits to the computation circuit or one or more memory bits provided from the memory array are all in a first logic state. In response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state, the controller can generate a control signal to disable at least one component of the computation circuit.