Network Accelerator for CIP Motion Control Latency
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Solution Overview
Problem
Current industrial control systems using EtherNet/IP for motion control applications face challenges in meeting the stringent time requirements for motion I/O connection processing due to memory bottlenecks, making it costly and impractical to upgrade all device processors with L2 cache, and manufacturers may hesitate to invest in new processors for an unproven market.
Innovation Solution
Implementing a hardware-based network accelerator with its own processor to speed up CIP communications between a motion controller and a motion drive, which intercepts and parses EtherNet/IP packets, stores data in memory locations, and provides interrupts to the host CPU, reducing the computational burden and enhancing processing power for network communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If device processors are upgraded with L2 cache to reduce memory bottlenecks, then CIP communication processing speed is improved, but device cost and system complexity increase
Solution Approach 1:
The patent divides the processing system into two segments: a host CPU that handles high-level control logic and a network accelerator that handles low-level packet processing. This segmentation allows the host CPU to maintain lower complexity while achieving fast CIP communication through the dedicated accelerator hardware.
Solution Approach 2:
The network accelerator acts as an intermediary between the Ethernet network and the host CPU. It intercepts CIP packets, parses them, and presents processed data to the CPU through interrupts, thereby speeding up communication without requiring the CPU itself to be upgraded with L2 cache.
2Loss of time
If all device processors are upgraded to high-performance processors, then motion I/O connection processing time is reduced, but system cost increases
Solution Approach 1:
The network accelerator performs self-service by autonomously handling packet interception, parsing, and data preparation. It manages its own memory locations and generates interrupts when data is ready, eliminating the need for expensive high-performance processors while reducing motion I/O processing time.
Solution Approach 2:
The patent replaces the mechanical approach of upgrading processors with additional hardware (network accelerator) that performs specific functions. This substitution achieves the same time reduction effect without the cost of high-performance processors.
3Productivity
If manufacturers invest in new processors for unproven market, then communication performance is improved, but manufacturing risk and cost increase
Solution Approach 1:
The network accelerator is designed as a universal component that can be integrated with existing host CPUs without requiring manufacturers to develop new processors. It provides multi-functionality by handling various CIP packet types and communication protocols, making it feasible for manufacturers to adopt without significant investment in new processor development.
Data Source
AI summary
An apparatus for accelerating communications over the Ethernet between a first processor and a second processor where the communications include CIP messages, the apparatus comprising a network accelerator that includes memory locations, the accelerator associated with the first processor and programmed to, when the second processor transmits a data packet to the first processor over the Ethernet, intercept the data packet at a first processor end of the Ethernet, extract a CIP message from the data packet, parse the CIP message to generate received data, store the received data in the memory locations and provide a signal to the first processor indicating that data for the first processor in stored in the memory locations.