Processing Device Buffer Ciphering System Bus Bottleneck
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Solution Overview
Problem
Conventional communication devices face challenges in achieving high data rates due to the system bus becoming a bottleneck, requiring significant dimensioning to handle sustained data rates, which leads to increased power consumption and latency.
Innovation Solution
A processing device with a buffer, ciphering device, and memory is configured to operate in deciphering and ciphering modes, reducing data transfers over the system bus by allowing direct data unit transfer between the buffer and memory through the ciphering device, thereby minimizing the load on the system bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred multiple times between buffer, memory and ciphering device over the system bus, then data processing can be performed, but the system bus becomes a bottleneck and power consumption increases
Solution Approach 1:
The patent combines the buffer and memory into a unified memory structure where the buffer is integrated within the memory device. This merging eliminates the need for separate data transfers between buffer and memory over the system bus, as the ciphering device can directly access both the buffer (for incoming/outgoing data) and memory (for ciphering keys and algorithms) through the same interface, thereby reducing bus traffic and power consumption while maintaining processing efficiency
2Speed
If the system bus is dimensioned to handle three times the maximum data rate, then sustained data rates can be achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the buffer function from the system bus architecture and integrates it directly into the memory device. This extraction removes the buffer-to-memory data transfer path from the system bus, eliminating the need to dimension the bus for three times the maximum data rate. The buffer remains functional for receiving and transmitting data, but its integration with memory allows the system bus to operate at the actual maximum data rate without excessive capacity
3Productivity
If multiple data transfers occur over the system bus for ciphering operations, then data can be processed, but latency increases
Solution Approach 1:
The patent implements preliminary action by pre-loading ciphering keys and algorithms into the memory device along with the buffer integration. This allows the ciphering device to immediately access all necessary resources without requiring separate data transfer operations. The buffer is pre-configured to receive data, and the memory is pre-populated with ciphering parameters, enabling the ciphering operation to proceed with minimal latency while maintaining high throughput
Data Source
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AI summary
The invention relates to a processing device (100) comprising a buffer (102) coupled to a system bus (104), a ciphering device (106) coupled to the system bus (104), and a memory (108) coupled to the ciphering device (106). The processing device (100) is configured to operate in at least one of a deciphering mode and a ciphering mode. When the processing device (100) is configured to operate in the deciphering mode, the ciphering device (106) is configured to receive a ciphered data unit directly from the buffer (102) over the system bus (104), decipher the ciphered data unit so as to obtain a deciphered data unit, and transfer the deciphered data unit to the memory (108). When the processing device (100) is configured to operate in the ciphering mode, the ciphering device (106) is configured to receive a data unit from the memory (108), cipher the data unit so as to obtain a ciphered data unit, and transfer the ciphered data unit directly to the buffer (102) over the system bus (104). Furthermore, the invention also relates to corresponding methods, a computer program, and a computer program product.