Wireless Ciphering Protocol Unit Buffer Memory Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for data ciphering in wireless communication systems, particularly in W-CDMA and HSPA, require multiple memory accesses, leading to delayed data processing due to the need to read, cipher, and store data in memory before transmission, which increases processing time and reduces data transmission speed.
Innovation Solution
A protocol processing unit implemented by hardware logic that performs simultaneous ciphering and transmission data processing, allowing ciphered data to be directly transmitted to the RF communication unit with a MAC header added, eliminating the need for intermediate memory storage and reducing memory access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is ciphered using software or hardware with memory access, then data can be stored and processed, but the processing time is delayed due to multiple memory access operations
Solution Approach 1:
The patent introduces an intermediary buffer memory that acts as a mediator between the cipher hardware and the main memory. The cipher hardware reads data from the buffer memory instead of directly from the main memory, performs ciphering operations, and writes results back to the buffer memory. This intermediary structure allows parallel operations and reduces the number of times the cipher hardware needs to access the main memory, thereby reducing data processing time while maintaining complete data processing.
Solution Approach 2:
The patent implements preliminary action by pre-loading data into the buffer memory before ciphering operations begin. The transmission data processing unit prepares data packets and loads them into the buffer memory in advance, so that when the cipher hardware needs to process the data, it is already available in the buffer memory. This eliminates waiting time for memory access during ciphering operations and reduces overall processing time while ensuring complete data processing.
2Reliability
If cipher hardware accesses memory multiple times to read and store data, then data can be processed completely, but the number of memory access operations increases, delaying data processing
Solution Approach 1:
The buffer memory serves as an intermediary that eliminates the need for the cipher hardware to repeatedly access the main memory. Data is loaded once into the buffer memory from the main memory, then the cipher hardware can read and write multiple times to the buffer memory without affecting the main memory access count. This intermediary approach maintains complete data processing while significantly improving data processing speed by reducing memory access operations.
Solution Approach 2:
The patent segments the memory system into two distinct parts: main memory for long-term storage and buffer memory for active processing. By dividing the memory access function between these two segments, the system allows the cipher hardware to operate frequently on data in the buffer memory segment without burdening the main memory segment with repeated access operations. This segmentation maintains data processing completeness while improving processing speed.
3Reliability
If data is transmitted through memory for ciphering, then data can be stored and retrieved, but the data transmission speed is reduced due to memory access delays
Solution Approach 1:
The buffer memory acts as an intermediary transmission channel between the main memory and the cipher hardware. Data is transferred once from main memory to buffer memory, then transmitted rapidly between the buffer memory and cipher hardware without involving the main memory in each transmission cycle. This maintains reliable data storage in the main memory while achieving high-speed data transmission through the buffer memory intermediary.
Solution Approach 2:
The patent adds a new dimension to the data transmission path by introducing the buffer memory as an intermediate layer. Instead of a single-dimensional path between main memory and cipher hardware, the data can now traverse through the buffer memory dimension, which is optimized for fast read/write operations. This dimensional change enables high-speed transmission while maintaining the reliability of main memory storage.
Data Source
AI summary
An apparatus for ciphering data in a wireless communication system. The apparatus includes a memory which stores data to be ciphered; a controller which outputs a cipher command for each layer of a wireless protocol; a protocol processing unit including a cipher hardware, which receives the cipher command outputted from the controller, reads data to be ciphered from the memory, ciphers the data and outputs the ciphered data, and a transmission data processing unit, which receives ciphered data that is directly outputted from the cipher hardware, adds a header for transmission and generates a data packet; and an RF communication unit which directly receives the generated data packet and transmits the received data packet.