Circuit Abstraction for Timing Path Analysis
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Solution Overview
Problem
Conventional floorplanning and circuit optimization tools for integrated circuit (IC) designs take a long time to complete and often produce poor quality results due to the rapid increase in size and complexity of IC designs, as well as stringent timing, area, and power budgets.
Innovation Solution
A circuit abstraction method that reduces the size of the circuit design by retaining only essential elements and identifiers for timing paths and side loads, allowing for efficient determination and updating of timing information during floorplanning and circuit optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional floorplanning and circuit optimization tools are used on full-scale IC designs, then complete timing analysis can be performed, but the tools take a very long time to complete and produce poor quality results
Solution Approach 1:
The patent segments the full circuit design into a smaller circuit abstraction that includes only the subset of circuit elements and nets relevant to timing analysis. This segmentation allows timing analysis to be performed on a manageable portion of the design, significantly reducing execution time while maintaining accuracy for critical timing paths.
Solution Approach 2:
The patent extracts essential timing-related information from the full circuit design by identifying and retaining only the circuit elements and nets that form timing paths and affect timing constraints. This extraction creates a simplified circuit abstraction that preserves timing accuracy while eliminating unnecessary complexity.
2Loss of information
If the full circuit design is used for timing analysis, then complete timing information can be obtained, but the circuit abstraction size becomes too large to handle efficiently
Solution Approach 1:
The patent applies local quality by differentiating between circuit elements that are part of timing paths and those that are not. Elements on timing paths are retained in full detail, while elements not affecting timing are excluded or represented by simplified side load models, creating a circuit abstraction with appropriate detail at each location.
Solution Approach 2:
The patent creates a simplified copy of the circuit design that captures only the essential timing characteristics. This copy includes the timing paths with full detail and side load representations for elements not directly on timing paths, providing a manageable abstraction that preserves timing information completeness.
3Reliability
If circuit elements not on timing paths are included in full detail, then complete circuit information is available, but the performance of floorplanning and circuit optimization deteriorates
Solution Approach 1:
The patent replaces detailed representations of circuit elements not on timing paths with simplified side load models. These side load representations are computationally inexpensive and sufficient for timing analysis purposes, dramatically improving performance while maintaining timing analysis reliability.
Solution Approach 2:
The patent applies partial action by including only the necessary portion of circuit elements in the detailed circuit abstraction. Elements not on timing paths are represented by simplified side load models rather than full detail, providing just enough information for accurate timing analysis without the computational burden of complete detail.
Data Source
AI summary
Systems and techniques for determining a set of timing paths for creating a circuit abstraction are described. During operation, an embodiment can receive a set of circuit elements in the circuit design that are candidates for optimization. Next, the embodiment can determine a set of timing paths by identifying critical timing paths in the circuit design whose delay is affected by a change in an input capacitance of a circuit element in the set of circuit elements. The embodiment can then identify a set of side loads based on the set of timing paths, and can create the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during optimization of the circuit element.