Circuit Board Cavity Structure for Adhesion and Etch Reliability
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Solution Overview
Problem
The existing semiconductor packages face issues with increased thickness due to vertical connections, adhesion problems between insulating layers, exposure of glass fibers causing defects, and reliability concerns due to etching during the de-smear process, which can lead to copper migration and warpage.
Innovation Solution
A circuit board design featuring a first and second insulating layer with different materials, a cavity in the second layer, and a dummy electrode to prevent etching, along with a protective layer to enhance adhesion and prevent warpage, while reducing signal transmission distance and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the de-smear process is performed to improve adhesion between the molding member and the circuit board, then adhesion is improved, but the lower surface of the cavity is etched together with the side wall, causing damage and reliability problems
Solution Approach 1:
The patent applies different etching resistances to different regions of the cavity. The side wall of the cavity is designed to be etched by the de-smear process to improve adhesion, while the lower surface is protected from etching. This localized differentiation of etching behavior resolves the contradiction between improving adhesion and preventing damage to the lower surface.
2Strength
If the de-smear process is performed to improve adhesion, then adhesion between molding member and circuit board is improved, but glass fibers in the thermosetting resin are exposed through the cavity, causing defects such as copper migration
Solution Approach 1:
The patent creates a localized etching pattern where only the side wall of the cavity is etched while the lower surface remains intact. This prevents glass fibers on the lower surface from being exposed, thereby avoiding copper migration defects while still achieving adhesion improvement through selective etching of the side wall.
3Adaptability or versatility
If multiple chips and interposers are stacked vertically to increase integration, then circuit integration is improved, but the thickness of the semiconductor package increases
Solution Approach 1:
The patent introduces a cavity dimension within the circuit board structure to accommodate multiple chips and interposers vertically. By creating a recessed space (cavity) in the circuit board, the patent enables vertical stacking of components while maintaining a compact overall thickness, thus resolving the contradiction between high integration and thin profile.
4Length of stationary object
If a cavity is formed in the circuit board to reduce thickness, then vertical thickness is reduced, but the adhesion between molding member and circuit board decreases without de-smear process
Solution Approach 1:
The patent applies selective etching to specific regions of the cavity - the side wall is etched to improve adhesion while the lower surface is protected. This localized etching approach enables the circuit board with cavity to achieve both thickness reduction and sufficient adhesion strength.
Data Source
Figure 1a
Figure 1b
Figure 1c
AI summary
A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a circuit pattern layer disposed between the first insulating layer and the second insulating layer, wherein the second insulating layer includes a cavity passing through upper and lower surfaces of the second insulating layer, and wherein the circuit pattern layer includes: an electrode pad disposed on a lower surface of the cavity; and a dummy electrode disposed on the lower surface of the cavity and spaced apart from the electrode pad and surrounding an outer side of the electrode pad.