Circuit Board Dummy Terminal for Electroplating Uniformity

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Solution Overview

Problem

The electroplating process in circuit board manufacturing often results in flash plating or skip plating, which decreases the yield and quality of the circuit board.

Innovation Solution

A manufacturing method for a circuit board that includes forming a patterned conductive layer with a dummy plating area, a plating seed layer, and a plating mask layer, where the dummy plating opening increases the plating area, reducing the likelihood of flash or skip plating by ensuring adequate coverage during the electroplating process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the electroplating process is applied to the circuit board, then the conductive terminals are formed, but flash plating or skip plating occurs which decreases the yield and quality

Engineering Contradiction:
Improveplating qualityVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a dummy terminal with a dummy plating area before the actual electroplating process. This dummy structure is prepared in advance to modify the plating field distribution, ensuring that the subsequent electroplating process achieves uniform coverage and prevents flash plating or skip plating defects.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy terminal acts as an intermediary element between the plating power supply and the actual conductive terminals. It mediates the electroplating process by redistributing the plating current and electric field, ensuring uniform plating deposition across all terminals while preventing harmful plating defects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the plating area is increased by adding dummy plating opening, then the occurrence of flash or skip plating is reduced, but the device complexity increases

Engineering Contradiction:
Improveplating uniformityVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the plating area into functional zones: the actual conductive terminal area and the dummy terminal area. This segmentation allows independent optimization of each zone, where the dummy zone specifically addresses plating uniformity without affecting the functional requirements of the actual terminals, thus managing complexity through functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy terminal structure serves multiple functions: it acts as a current distributor to prevent flash plating, a field uniformity modifier to prevent skip plating, and a process control element to ensure consistent plating thickness. By consolidating these functions into a single structural element, the patent avoids the need for multiple separate components, thereby managing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the plating area in the electroplating process, thereby reducing the occurrence of flash or skip plating and improving the yield and quality of the circuit board.

Implementation Method 1

forming a plating layer within the plating opening and the dummy plating opening

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11219130B2Circuit board and manufacturing method thereof
Publication Date: 2022.01.04 UNIMICRON TECH CORP
  • US11219130B2 patent drawing
  • US11219130B2 patent drawing
  • US11219130B2 patent drawing

AI summary

A circuit board including a substrate, a patterned conductive layer, a patterned insulating layer, a conductive terminal, and a dummy terminal is provided. The patterned conductive layer is disposed on the substrate. The patterned insulating layer is disposed on the substrate and at least covers a portion of the patterned conductive layer. The conductive terminal is disposed on the patterned conductive layer and has a first top surface. The dummy terminal is disposed on the patterned conductive layer and has a second top surface. A first height between the first top surface and the substrate is greater than a second height between the second top surface and the substrate.