Circuit Carrier Redistribution Structure for Thinner Chip Packaging
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Solution Overview
Problem
Conventional semiconductor chip packaging methods result in thick, costly carriers due to the use of silicon substrates and through silicon vias, making miniaturization and cost reduction challenging while maintaining manufacturing simplicity.
Innovation Solution
A manufacturing method for a circuit carrier that omits the silicon substrate by forming a fine redistribution structure with conductive patterns and vias on a temporary carrier, transferring it to another carrier with release layers, and bonding it to a core layer with through core vias, allowing for reduced thickness and cost without solder balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon substrates and through silicon vias are used in conventional packaging techniques, then reliability and conductivity are maintained, but the carrier becomes thick and costly
Solution Approach 1:
The patent extracts and removes the silicon substrate from the conventional packaging structure, replacing it with an organic carrier substrate. This extraction eliminates the need for through silicon vias and reduces the overall carrier thickness while maintaining the essential conductivity and reliability functions through alternative conductive structures.
Solution Approach 2:
The patent changes the material parameter from silicon-based substrates to organic carrier substrates, fundamentally altering the structural composition. This parameter change enables thinner carrier design while preserving electrical conductivity through the use of conductive patterns and vias in the organic substrate.
2Reliability
If silicon substrates and through silicon vias are used in conventional packaging techniques, then conductivity is maintained, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon substrates with more cost-effective organic carrier substrates. This substitution uses cheaper materials that can achieve the same conductivity function through printed or patterned conductive structures, significantly reducing manufacturing costs while maintaining electrical performance.
Solution Approach 2:
The patent creates a functional copy of the conductivity network using conductive patterns and vias in the organic substrate, replicating the electrical connectivity function of silicon TSVs but with simpler, less expensive manufacturing processes such as printing or lamination techniques.
3Strength
If conventional packaging substrates like PCB are used, then structural support is provided, but the entire size and through core via dimension cannot be minimized
Solution Approach 1:
The patent segments the carrier structure into functional layers within an organic substrate, separating the structural support function from the conductive function. This segmentation allows for miniaturization of through core vias and overall size while maintaining structural integrity through the organic substrate's inherent strength properties.
Solution Approach 2:
The patent employs thin-film organic carrier substrates that provide structural support in a minimized form factor. These thin film structures replace bulky PCB constructions, enabling reduction of the entire size and via dimensions while maintaining the necessary structural support for chip packaging.
Data Source
AI summary
A manufacturing method of a circuit carrier with a chip mounted thereon is provided. A fine redistribution structure is formed over a first temporary carrier. A first release layer is applied on the first temporary carrier. A plurality of conductive connectors is formed on the fine redistribution structure to form a first portion. The fine redistribution structure and the conductive connectors are transferred to a second temporary carrier. The second temporary carrier is provided with a second release layer. The first temporary carrier is removed after the conductive connectors inserted into the second release layer. A surface finishing process is performed on the fine conductive pattern distributed on the fine redistribution structure to form a surface finishing layer. The fine redistribution structure and the surface finishing layer formed thereon are adhered to a third temporary carrier through a third release layer. The first portion is disposed on a second portion.