Digital Circuit Clock Speed via Flip-Flop to Latch Conversion
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Solution Overview
Problem
Current computer-aided design tools provide limited support for improving clock speed in digital circuits after the design has been placed and routed, often requiring compromises that do not satisfy timing constraints, leading to suboptimal clock rates.
Innovation Solution
A graph-based approach is used to represent the circuit design, where nodes represent flip-flops and edges represent data input and output couplings with associated delay values. By determining the smallest period that allows replacement of selected flip-flops with latches without creating negative cycles, the circuit design is modified to increase clock speed, with the process involving the generation of a graph, selection of a path, and replacement of flip-flops with latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock speed is increased to improve productivity, then the clock rate increases, but the timing constraints of critical paths may not be satisfied
Solution Approach 1:
The patent changes the state parameter of selected flip-flops from edge-triggered to transparent latch mode, transforming them from synchronous storage elements to transparent memory elements. This parameter change allows the circuit to operate at higher clock speeds while maintaining timing constraints by eliminating the rigid edge-triggered synchronization requirement.
Solution Approach 2:
The patent introduces dynamic reconfigurability by allowing selective conversion of flip-flops to latches based on critical path analysis. The system dynamically adjusts the behavior of memory elements in the circuit, converting edge-triggered flip-flops to transparent latches in specific locations where it optimizes timing performance while maintaining functionality.
2Productivity
If flip-flops are replaced with latches to increase clock speed, then the clock rate improves, but the circuit complexity increases
Solution Approach 1:
The patent applies local quality by selectively converting only specific flip-flops to latches based on critical path analysis, rather than converting all flip-flops uniformly. This localized approach optimizes timing performance in critical paths while preserving edge-triggered behavior in non-critical paths, thereby minimizing the increase in circuit complexity.
Solution Approach 2:
The patent segments the circuit into critical paths and non-critical paths, applying different optimization strategies to each. By identifying and targeting only the critical paths for flip-flop-to-latch conversion, the system achieves clock speed improvement without unnecessarily increasing complexity throughout the entire circuit.
3Reliability
If edge-triggered flip-flops are used to ensure timing constraints are met, then reliability is maintained, but the clock speed is limited
Solution Approach 1:
The patent changes the operational parameter of selected flip-flops from edge-triggered mode to transparent latch mode. This parameter change eliminates the strict edge-triggered timing requirements, allowing the circuit to operate at higher clock speeds while still satisfying timing constraints through the transparent latch behavior that allows data to pass through when enabled.
Data Source
AI summary
Various approaches for improving clock speed for a circuit design. In one embodiment, a graph having nodes and edges that represent the circuit design is generated. The nodes represent flip-flops of the design, the edges represent couplings of data inputs and outputs of the flip-flops, and the edges have associated delay values for respective durations of signal delays of the couplings. A smallest period is determined for which subtracting each delay value from the smallest period and associating the difference with the associated edge does not create a negative cycle in the graph. A path in the graph is selected, the path including selected flip-flops and connecting edges. The circuit design is modified by replacing the selected flip-flops with latches, and the smallest period is output.