Circuit Data Bus Visualization via Selection Criteria Filtering
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Solution Overview
Problem
The increasing complexity and size of circuit designs make it difficult for designers to analyze and debug data flows, as existing methods provide overly detailed schematics that obscure important data movements and computations.
Innovation Solution
A method and system that determine and visually represent only the data buses and elements of interest in a circuit design, excluding those that do not satisfy selection criteria, using top-down and edge-based bus tracking approaches to generate a graphical data flow view, allowing designers to focus on impactful data flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If detailed schematics are provided to show all data buses in a circuit design, then completeness of information is improved, but complexity of analysis and debugging deteriorates
Solution Approach 1:
The patent extracts and displays only the data buses and elements that satisfy user-defined selection criteria, separating them from the complete circuit design. This extraction approach maintains information completeness for relevant components while eliminating irrelevant complexity, allowing designers to focus on specific data paths of interest without being overwhelmed by the entire design.
Solution Approach 2:
The patent segments the complete circuit design into multiple graphical representations based on selection criteria. Each graphical representation displays a subset of data buses and elements that meet specific conditions, dividing the complex overall design into manageable segments that can be analyzed independently while preserving the complete information structure.
2Loss of information
If all data buses are displayed in the graphical representation, then information completeness is improved, but readability and understanding of critical data paths deteriorates
Solution Approach 1:
The patent extracts only the data buses and elements that satisfy selection criteria from the complete circuit design, displaying them in a simplified graphical representation. This extraction maintains completeness of information for relevant components while improving readability by eliminating irrelevant elements that would obscure critical data paths.
Solution Approach 2:
The patent applies different display qualities to different parts of the circuit design based on their relevance. Data buses and elements that satisfy selection criteria are displayed with full detail and visibility, while those that do not satisfy the criteria are excluded or displayed with reduced prominence, creating a locally optimized visualization that enhances readability where it matters most.
3Reliability
If comprehensive graphical representation of all circuit elements is provided, then analysis coverage is improved, but time to process and display data deteriorates
Solution Approach 1:
The patent performs preliminary filtering of data buses and elements based on selection criteria before generating the graphical representation. By pre-processing the circuit design data to identify and mark elements that satisfy the criteria, the system reduces the amount of data that needs to be processed and displayed, thereby maintaining comprehensive analysis coverage while significantly reducing processing and display time.
Solution Approach 2:
The patent applies partial action by processing and displaying only the portion of the circuit design that satisfies selection criteria, rather than processing the entire design. This partial processing approach maintains sufficient analysis coverage for the relevant components while reducing overall processing time, as the system performs exactly the amount of work necessary to achieve the analysis goal without excess.
Data Source
AI summary
Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.