Numerical Optimization for Circuit Delay, Area, and Leakage Power
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Solution Overview
Problem
Current circuit synthesis approaches are inefficient and produce poor quality results due to inaccurate delay modeling and failure to optimize for leakage power, area, and delay, especially in large circuit designs with multiple process corners and modes.
Innovation Solution
The method involves iterative numerical delay optimization, total negative slack based buffering, and worst negative slack touchup optimization, combined with area and leakage power optimization by progressively decreasing threshold voltage, using a technology library with discretized non-linear delay models to select optimal gate sizes and minimize leakage power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative trial-and-error based circuit synthesis approaches are used to optimize cell sizes, then timing constraints can be checked and satisfied, but the computational time required becomes excessively long and the quality of results deteriorates for large circuit designs
Solution Approach 1:
The patent transforms the discrete trial-and-error cell sizing process into a continuous optimization problem by introducing threshold voltage as a continuous parameter. The nonlinear delay model expresses cell delay as a function of threshold voltage, allowing gradient-based optimization algorithms to efficiently find optimal cell sizes without exhaustive iteration across multiple process corners and modes.
Solution Approach 2:
The patent replaces the mechanical trial-and-error iteration process with a mathematical optimization framework. By formulating the synthesis problem as minimizing a cost function subject to timing constraints using nonlinear programming, the system substitutes computational brute force with analytical optimization methods that converge faster and produce higher quality results.
2Loss of energy
If multiple threshold voltage gates are used to optimize leakage power, then leakage power can be reduced, but the complexity of the optimization process increases due to the need to balance delay and leakage tradeoffs
Solution Approach 1:
The patent introduces threshold voltage as an additional continuous optimization parameter alongside cell size. The nonlinear delay model incorporates threshold voltage effects, allowing the optimizer to simultaneously determine optimal cell dimensions and threshold voltage selections. This unified parameter approach reduces leakage power while managing complexity through mathematical formulation rather than discrete enumeration.
3Measurement precision
If accurate nonlinear delay modeling is used to represent actual cell delays, then timing accuracy improves, but the computational expense of checking timing constraints across many process corners and modes increases
Solution Approach 1:
The patent replaces exhaustive timing verification across multiple process corners and modes with a mathematical optimization framework that inherently accounts for variability. The nonlinear programming formulation integrates timing constraints with the delay model, allowing the optimizer to find solutions that satisfy timing requirements without requiring separate verification iterations for each process corner.
Solution Approach 2:
The patent performs preliminary formulation of the optimization problem that embeds timing constraints directly into the mathematical model. By pre-defining the nonlinear delay model and timing constraint relationships, the system eliminates the need for repeated timing analysis during the optimization process, reducing computational expense while maintaining accuracy.
Data Source
AI summary
Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.