Circuit Design Support Device for Buffer Reduction via Access Order Reordering
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Solution Overview
Problem
Conventional semiconductor integrated circuit design faces challenges in efficiently eliminating redundant buffers due to the inability to change the order of write and read access addresses, leading to increased circuit scale and design time.
Innovation Solution
A circuit design support device that analyzes behavior description code to determine and alter the order of write and read access addresses, matching them to reduce buffer requirements and circuit scale.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the order of write access addresses and read access addresses is not changed, then the buffer size increases to accommodate all array elements, but the circuit scale becomes larger and design time increases
Solution Approach 1:
The patent applies dynamics by making the access order flexible and changeable rather than fixed. The access order changing unit dynamically adjusts the order of write access addresses and read access addresses based on analysis of the behavior description code, allowing the system to adapt to different access patterns and eliminate redundant buffers accordingly
Solution Approach 2:
The patent changes the parameter of access order by analyzing the behavior description code to determine the actual access patterns, then modifying the order of write and read access addresses to match these patterns. This parameter change enables the elimination of redundant buffers while maintaining correct data access semantics
2Quantity of substance
If the order of write access addresses and read access addresses is not changed, then all array elements require buffer storage, but the design time increases due to inability to optimize buffer elimination
Solution Approach 1:
The patent applies preliminary action by performing code analysis to determine access orders before the actual buffer allocation and circuit generation. The access order determining unit and access order changing unit proactively analyze and optimize the access patterns in advance, enabling buffer elimination decisions to be made before synthesis, thus reducing both buffer requirements and overall design time
Solution Approach 2:
The patent implements feedback by using the determined access orders from code analysis to guide the buffer elimination process. The system continuously refines the access order configuration based on the analyzed behavior description code, using this feedback information to optimally eliminate redundant buffers while maintaining correctness
Data Source
AI summary
A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and an order of using each read access address when the behavior description code is executed. Further, the processing part performs either one of a write access order changing process to change the order of using the write access addresses when the behavior description code is executed based on the order of using the read access addresses and a read access order changing process to change the order of using the read access addresses when the behavior description code is executed based on the order of using the write access addresses.