Automated Circuit Design via Active Set Optimization
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Solution Overview
Problem
Existing circuit design optimization methods struggle to produce transistor-level details that are adaptable across a wide range of scenarios, often resulting in infeasible solutions due to limitations in solving optimization problems over multiple scenarios, which can lead to incomplete definitions of circuit behavior.
Innovation Solution
The implementation of an active set optimization problem solving methodology that incorporates equalities into the constraint set and classifies variables as scenario-independent or dependent, allowing for the identification of specific numeric values for transistor dimensions that maintain performance criteria across various operating scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If optimization problem solving is performed over a large number of scenarios to ensure circuit adaptability, then the reliability and adaptability of the circuit design is improved, but the computational complexity and difficulty of obtaining a global solution increases
Solution Approach 1:
The patent segments the set of all scenarios into a subset of scenarios for solving the optimization problem. By selecting a representative subset rather than solving across all possible scenarios, the method reduces computational complexity while maintaining circuit adaptability. The segmentation allows the optimizer to find a global solution over the subset that satisfies performance criteria across all scenarios.
Solution Approach 2:
The patent performs preliminary action by first solving the optimization problem over a selected subset of scenarios to obtain transistor level details, then verifying feasibility across the remaining scenarios. This preliminary solving approach allows the method to establish a candidate solution efficiently before validating its robustness across the full scenario space.
2Ease of manufacture
If the number of scenarios is limited to reduce computational difficulty, then the ease of solving optimization problems is improved, but the reliability of the circuit design across all scenarios deteriorates
Solution Approach 1:
The patent implements feedback by verifying whether the transistor level details obtained from solving over a subset of scenarios are feasible across all scenarios. If infeasibilities are detected in scenarios outside the optimization subset, the method provides feedback to adjust the design or re-solve the optimization problem, ensuring the final design meets reliability requirements across the full scenario space.
Solution Approach 2:
The patent applies dynamics by allowing the subset of scenarios to be adjusted and refined based on verification results. The method dynamically adapts the optimization approach by re-solving with modified constraints or adjusted scenario subsets until a feasible global solution is achieved, balancing computational ease with design reliability.
3Manufacturing precision
If a global transistor level definition is sought across all scenarios, then the completeness of circuit definition is improved, but the computational resources and time required increase significantly
Solution Approach 1:
The patent segments the comprehensive circuit definition task into two phases: first obtaining transistor level details by solving optimization over a subset of scenarios, then verifying completeness across all scenarios. This segmentation achieves complete circuit definition without requiring exhaustive optimization across all scenarios simultaneously, significantly reducing computational time while maintaining definition completeness.
Solution Approach 2:
The patent applies partial action by solving the optimization problem over a selected subset of scenarios rather than all scenarios. This partial solving approach is sufficient to obtain the global transistor level definition, as the subset is carefully chosen to be representative. The method avoids excessive computation by not solving over the full scenario space when a representative subset achieves the same design completeness.
Data Source
AI summary
A method is described that involves solving a family of equations for a circuit being designed over a subset of operational scenarios, thereby producing numeric values for design parameters of the circuit. The family of equations is enhanced with the numeric values are solved over a second subset of the operational scenarios. A design for the circuit that includes the numeric values is produced.