Circuit Design Optimization Using Clustering and Low-Rank Matrix Approximation

The patent segments the high-dimensional design space into multiple lower-dimensional subspaces using clustering algorithms. By fitting response surface models in these smaller subspaces rather than the entire design space, the computational complexity is dramatically reduced while maintaining modeling accuracy. Each cluster requires fewer sampling points and model coefficients to be computed, directly addressing the contradiction between accuracy and computational cost.

The patent transforms the traditional approach by adding a clustering dimension to the design space. Instead of directly fitting a global model in n-dimensional space, the method introduces a cluster assignment dimension, creating a hierarchical structure where models are fitted in (n+k)-dimensional space but with significantly reduced complexity due to the localized nature of each cluster. This dimensional transformation enables accurate modeling without the exponential computational cost of conventional global quadratic models.

The patent divides the design space into multiple clusters, allowing the use of fewer sampling points per cluster while maintaining overall model accuracy. Instead of requiring numerous sampling points across the entire design space, the segmentation approach concentrates sampling efforts within localized regions, reducing the total number of simulation runs needed and thereby decreasing design process time while preserving modeling fidelity.

The patent applies partial action by fitting response surface models only in relevant local regions (clusters) rather than attempting to model the entire design space uniformly. This selective approach uses sampling points only where they are most needed, avoiding the time-consuming requirement of exhaustive sampling across all possible design regions, thus reducing design process time while maintaining accuracy in critical areas.

The patent segments the large-scale circuit design space into multiple manageable clusters, making the optimization problem computationally tractable. By dividing the comprehensive design space into smaller regions and fitting local response surface models to each, the method maintains adaptability and versatility across the entire design space while reducing the computational complexity of each individual model fitting operation, enabling large-scale circuit design optimization.

The patent introduces clustering as an additional organizational dimension that structures the large-scale design problem. This dimensional transformation converts a single complex high-dimensional optimization problem into multiple simpler localized problems, maintaining comprehensive design space coverage through the cluster hierarchy while making the overall computational complexity manageable through parallel processing and reduced per-cluster complexity.