Circuit Design Partitioning for Debugging Logic Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The placement and routing of circuit designs involving application logic and debugging logic on Stacked Silicon Interconnect (SSI) devices face challenges due to the large number of connections required between different super logic regions (SLRs), leading to routing congestion and limited inter-SLR connections, which can result in unfeasible implementations.
Innovation Solution
A method that partitions the circuit design into separate integrated circuit (IC) dies, initially ignoring debugging logic connections during partitioning to reduce inter-die connections, and then adjusts these connections to minimize wire length by placing application logic and debugging logic within the same partition, using bi-partite matching algorithms to optimize routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the circuit design is partitioned into multiple IC dies to reduce inter-die connections, then the routing congestion is alleviated, but the total wire length increases due to connections between partitions
Solution Approach 1:
The circuit design is partitioned into multiple partitions that are mapped to different IC dies. This segmentation reduces the number of connections that need to be routed between dies, thereby alleviating routing congestion on each individual die. The partitioning process strategically groups logic elements to minimize inter-die connectivity requirements.
Solution Approach 2:
Instead of keeping all debugging logic connections within a single die (which would cause congestion), the approach inverts the strategy by deliberately distributing connections across multiple dies. The system accepts increased inter-die wire length as a trade-off to achieve feasible routing density on each die.
2Adaptability or versatility
If debugging logic is kept separate from application logic partitions, then routing flexibility is improved, but the number of inter-partition connections increases
Solution Approach 1:
The method merges debugging logic with application logic within the same partitions. By co-locating debugging logic near the application logic it serves, the number of inter-partition connections is reduced. This merging maintains routing flexibility while minimizing the quantity of inter-partition connectivity required.
3Ease of manufacture
If inter-IC connections are minimized through partitioning, then manufacturing feasibility is improved, but the optimization of routing requires complex algorithms
Solution Approach 1:
The partitioning and placement algorithms perform preliminary optimization before the actual manufacturing process. By pre-calculating the optimal partition assignments and connection mappings, the system minimizes inter-IC connections in advance, making the subsequent manufacturing process more feasible and straightforward.
Data Source
AI summary
Processing a circuit design that specifies application logic and debugging logic includes partitioning the circuit design. Each partition includes a part of the application logic and a part of the debugging logic, each partition is specified for implementation on a respective IC die, and the circuit design specifies connections between a part of the application logic in one partition and a part of the debugging logic in another partition. The connections between the part of the application logic in the one partition and the part of the debugging logic in the other partition are changed to connections from the part of the application logic in the one partition to a part of the debugging logic in the one partition. The part of the application logic and the part of the debugging logic of each partition are placed and routed on the respective IC die.