Automated Circuit Design Verification via Finite State Machine Generation
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Solution Overview
Problem
The increasing complexity of integrated circuits makes it difficult to verify circuit designs efficiently, consuming significant time and resources, as existing methods rely heavily on manual simulation and measurement criteria like coverage, which can be incomplete and prone to errors.
Innovation Solution
A computing system that generates a functional coverage model from hardware description language (HDL) code, converting it into a formal language model and finite state machine, allowing for automated verification of circuit designs, reducing manual effort and errors by providing a comprehensive set of events and conditions for validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual simulation and coverage-based verification methods are used, then verification can be performed with existing tools, but verification time and resource consumption increase significantly
Solution Approach 1:
The patent replaces manual simulation-based verification with automated formal verification methods. The system automatically generates finite state machines from HDL code, performs exhaustive state exploration, and verifies circuit correctness without relying on manual test case creation and simulation, thereby reducing verification time while maintaining or improving verification completeness.
Solution Approach 2:
The verification system performs self-verification by automatically analyzing its own generated finite state machines and coverage models. The system can autonomously determine whether all states and transitions have been verified and generate additional test cases if coverage is insufficient, reducing reliance on external manual verification efforts.
2Adaptability or versatility
If manual coverage model creation is used, then flexibility in defining coverage criteria is maintained, but human errors increase and automation extent decreases
Solution Approach 1:
The patent replaces manual creation of coverage models with automated generation from HDL source code. The system automatically parses HDL code, identifies functional components, and generates finite state machines and coverage models without human intervention, eliminating manual errors while maintaining the ability to define comprehensive coverage criteria through systematic code analysis.
Solution Approach 2:
The patent introduces finite state machines as an intermediary representation between HDL code and coverage models. This intermediate formal representation enables automated translation from hardware description to verification models, bridging the gap between design code and verification requirements while maintaining adaptability to different design styles and complexities.
3Reliability
If comprehensive verification coverage is pursued, then verification quality improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent segments the verification process into distinct modular components: HDL code parsing, finite state machine generation, coverage model creation, test case generation, and verification execution. Each component handles a specific aspect of verification, making the overall complex process manageable and maintainable while achieving comprehensive coverage through systematic exploration of all states and transitions.
Solution Approach 2:
The patent transforms verification from simulation-based time-domain analysis to formal state-space analysis by changing the fundamental parameter from temporal simulation steps to discrete state transitions. This parameter change enables exhaustive verification of all possible circuit states and transitions, ensuring comprehensive coverage without the resource constraints of lengthy simulations.
Data Source
AI summary
Provided are a method of generating a functional coverage model from a hardware description language (HDL) code for a circuit design and performing verification of the circuit design by using the functional coverage model, and a computing system in which the method is performed.