Circuit Design Automation Using Genetic and Reinforcement Learning
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Solution Overview
Problem
Current circuit design automation algorithms fail to efficiently generate optimal circuit structures and optimize transistor sizes, particularly due to neglecting process variations and characteristics of CMOS processes, leading to reduced performance and increased design time.
Innovation Solution
A circuit design method utilizing a genetic algorithm for generating candidate circuit structures and a reinforcement learning algorithm for optimizing transistor sizes based on analysis of multiple process corners, effectively reflecting CMOS process characteristics and ensuring target performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional circuit structure search algorithms are used, then circuit topology can be generated, but the search speed and efficiency are reduced because the algorithms do not reflect CMOS process characteristics
Solution Approach 1:
The patent applies local quality by differentiating the treatment of PMOS and NMOS transistors based on their specific CMOS process characteristics. The algorithm assigns different placement preferences and sizing rules to PMOS and NMOS devices, reflecting their distinct electrical properties and process behavior. This localized differentiation improves both search efficiency and reliability by making the generation process aware of specific device characteristics rather than treating all transistors uniformly.
2Manufacturing precision
If conventional transistor size optimization algorithms are used, then optimization can be performed, but the optimized circuit may not operate normally under process variations
Solution Approach 1:
The patent implements preliminary action by performing worst-case corner analysis during the transistor sizing optimization phase. Before finalizing the circuit design, the algorithm evaluates performance across multiple process corners (FF, SS, FS, SF) and adjusts transistor sizes to ensure robustness against process variations. This preliminary stress testing and optimization prevents operational failures under real-world process variations.
Solution Approach 2:
The patent applies parameter changes by systematically varying transistor width and length parameters during optimization to achieve robust performance. The algorithm adjusts device dimensions based on sensitivity analysis and worst-case corner simulations, modifying physical parameters to compensate for process variations. This dynamic parameter adjustment ensures the circuit meets performance specifications across all process corners.
3Ease of manufacture
If pre-built libraries or building blocks are used, then certain types of circuits can be applied, but only limited circuit types are supported
Solution Approach 1:
The patent implements universality by creating a generalized circuit generation algorithm that can handle multiple circuit types and topologies through a unified framework. Rather than relying on pre-built libraries limited to specific circuit types, the algorithm uses configurable templates and rules that can be adapted to generate various analog and mixed-signal circuits. This universal approach maintains ease of implementation while significantly expanding circuit type applicability.
4Reliability
If automated circuit design is not performed, then expert-designed circuits achieve good performance, but design time and cost are high
Solution Approach 1:
The patent applies self-service by implementing an automated circuit generation and optimization system that performs design tasks independently without requiring expert intervention. The algorithm autonomously generates candidate circuits, optimizes transistor sizes, evaluates performance, and iterates to find optimal solutions. This self-service capability achieves performance comparable to expert-designed circuits while dramatically reducing design time and cost.
Solution Approach 2:
The patent implements feedback through iterative optimization where circuit performance is evaluated and used to guide subsequent design adjustments. The algorithm continuously monitors performance metrics, compares them against targets, and automatically adjusts circuit parameters to improve performance. This closed-loop feedback mechanism enables automated systems to achieve expert-level performance through systematic refinement.
Data Source
AI summary
Proposed is a circuit design method and device that automatically designs circuits by generating candidate circuit structures and optimizing transistor sizes. According to the circuit design method and device, design time and cost are reduced, and circuit performance is improved. The circuit design method may comprise: generating, by a processor, a candidate circuit structure by executing a genetic algorithm based on a gene and associated with a circuit topology graph; and optimizing, by the processor, a transistor size of the candidate circuit structure by executing a reinforcement learning algorithm based on analysis of multiple process corners.