Behavioral Circuit Design Partitioning for Verification Bottlenecks
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Solution Overview
Problem
The increasing complexity and size of microelectronic circuits due to decreasing feature sizes lead to longer manufacturing cycles and challenges in physical design and verification, particularly in optimizing die size and timing verification, resulting in inefficient design verification processing times.
Innovation Solution
A method for design partitioning at the behavioral circuit design level that involves parsing hardware descriptive language, tracing signal dependencies, removing existing hierarchies, and creating a flattened circuit design hierarchy according to partition specifications, allowing for efficient analysis and optimization of circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If optimal physical placement of circuit design sections is performed from a purely geometric perspective, then die size is minimized, but timing verification becomes intractable due to non-optimized hierarchies
Solution Approach 1:
The patent applies segmentation by dividing the circuit design into multiple hierarchical levels and partitions. The verification process is segmented to operate on smaller, manageable subsets of the design rather than the entire circuit at once. This allows timing verification to be performed on partitioned designs with reduced complexity while maintaining verification completeness across the full design.
Solution Approach 2:
The patent introduces a new dimension to the verification process by adding hierarchical abstraction levels. Instead of verifying the entire flat design at once, the verification operates across multiple dimensions - from detailed gate-level views up to architectural-level abstractions. This dimensional approach allows geometric optimization at lower levels while performing timing verification at higher abstraction levels.
2Adaptability or versatility
If circuit design size increases to add functionality, then product capabilities improve, but manufacturing cycles lengthen due to increased processing steps
Solution Approach 1:
The patent applies preliminary action by performing hierarchical partitioning and verification setup before the actual timing verification and manufacturing processes. The design is pre-processed into hierarchical partitions with verified interfaces, so that subsequent verification steps can proceed more efficiently. This preliminary structuring reduces the overall verification time for complex, functional-rich designs.
Solution Approach 2:
The patent changes verification parameters by operating at multiple levels of abstraction rather than a single detailed level. At higher hierarchical levels, verification uses abstracted timing parameters and interface specifications, while at lower levels, detailed gate-delay parameters are used. This parameter transformation allows verification of large, functional circuits without linearly increasing processing time.
3Quantity of substance
If smaller individual silicon die size is used to fit more chips on a wafer, then cost per die decreases, but design verification becomes more difficult due to constrained physical space
Solution Approach 1:
The patent applies segmentation by dividing the verification task into hierarchical partitions that correspond to physical design blocks. Each partition can be verified independently with its own timing constraints and interface specifications. This segmentation makes verification of densely packed, small-die designs manageable by breaking down the complex interconnections into smaller, verifiable units.
Solution Approach 2:
The patent introduces hierarchical interface specifications as intermediaries between different design partitions. These interface contracts serve as mediators that define timing and functional requirements without requiring detailed knowledge of internal partition implementations. This intermediary layer simplifies verification of small, densely integrated circuits by abstracting away complex internal timing relationships.
Data Source
AI summary
A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.