Automated Circuit Design Replication for Intermittent Error Debugging
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Solution Overview
Problem
Current circuit design and simulation tools face challenges in debugging complex integrated circuits, particularly in reproducing intermittent errors and efficiently verifying the correctness of designs due to the complexity and size of modern ASICs, which traditional methods struggle to handle effectively.
Innovation Solution
A method involving the capture of initial condition signals and input signals from a chip, which are then used to replicate the circuitry for debugging purposes, allowing for the preservation of functionality while facilitating modifications for simplifying the debugging process, including the use of logic replication, snapshot solutions, and time division multiplexer techniques to recreate error conditions for simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional simulation tools and techniques are used to verify complex ASIC designs, then the verification process can be performed, but the complexity and size of modern ASICs make it difficult to solve verification problems effectively
Solution Approach 1:
The patent creates a replica of the original circuit design in a different technology platform (FPGA). This copy allows verification of the design without being constrained by the complexity of the original ASIC implementation. The replica is synthesized from the same HDL code but mapped to a FPGA architecture, enabling easier debugging and verification while maintaining functional equivalence.
Solution Approach 2:
The patent introduces an intermediate verification platform (FPGA) that mediates between the original ASIC design and the verification process. This intermediary allows designers to verify complex ASIC designs using FPGA-based tools and techniques that are more manageable than direct ASIC verification, thus resolving the contradiction between verification reliability and design complexity.
2Reliability
If prototype boards with multiple ICs are built to verify ASIC designs, then verification can be performed, but debugging becomes difficult and time-consuming
Solution Approach 1:
Instead of building physical prototype boards with multiple ICs, the patent creates a virtual copy of the circuit in an FPGA device. This digital replica eliminates the need for physical prototyping and associated debugging challenges, significantly reducing the time required to verify and debug designs while maintaining verification effectiveness.
Solution Approach 2:
The patent replaces the mechanical/physical debugging process (probe boards, logic analyzers, JTAG debugging of multiple ICs) with a software-based debugging approach in the FPGA domain. This substitution eliminates the time-consuming physical debugging steps while preserving the ability to verify design correctness.
3Difficulty of detecting and measuring
If logic analyzers and JTAG techniques are used to debug hardware designs, then error detection is possible, but the process is difficult and often not effective for intermittent errors
Solution Approach 1:
The patent creates a replica of the original design in FPGA that can be debugged using standard FPGA debugging tools. This copy provides the same error detection capability as physical hardware debugging but with much greater ease of operation, as FPGA debugging tools offer superior visibility and control compared to logic analyzers and JTAG techniques.
Solution Approach 2:
The patent performs verification and debugging in the FPGA replica before final ASIC fabrication. This preliminary action allows errors to be detected and fixed in a more accessible environment, avoiding the need for difficult post-fabrication debugging of the actual ASIC hardware.
4Difficulty of detecting and measuring
If simulators are used to debug errors, then errors can be analyzed, but errors that have already occurred are difficult to repeat and reconstruct
Solution Approach 1:
The patent creates a functional copy of the original design in FPGA that can be stimulated with the same inputs that caused the original error. This replica allows reliable reproduction of intermittent errors that are difficult to capture in physical hardware or original simulation, as the FPGA implementation can be re-run with recorded stimulus sequences.
Data Source
AI summary
Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described.