Circuit Design Verification Apparatus for Missing Assertion Detection
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Solution Overview
Problem
In electrical circuit design, it is challenging to detect and address missing assertions, as existing support tools may fail to identify them, leading to incomplete assertion descriptions and potential design failures.
Innovation Solution
A circuit design verification apparatus and program that performs automated analysis of assertion descriptions and signal lists, creating a scheme to identify missing assertions and recommend necessary amendments, ensuring these are reflected in the display and updated accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automated analysis is performed to identify missing assertions, then assertion coverage completeness is improved, but analysis time and computational resources increase
Solution Approach 1:
The system performs preliminary automated analysis of the circuit design to generate a scheme representing signal transitions and assertion coverage before the designer finalizes the assertion description. This advance analysis identifies potential missing assertions early in the design process, allowing designers to address coverage gaps before implementation, thus improving completeness without adding time to the final verification stage.
Solution Approach 2:
The patent introduces an intermediary scheme (graph structure) that mediates between the circuit design and the assertion description. This scheme acts as a computational model that can be automatically analyzed to identify coverage gaps, serving as a bridge that enables efficient automated verification without requiring direct complex analysis of the full circuit design and assertion set.
2Measurement precision
If comprehensive assertion analysis is performed, then detection accuracy of missing assertions is improved, but device complexity increases
Solution Approach 1:
The verification tool is segmented into distinct functional modules: a scheme generation module that creates the transition model, a coverage analysis module that identifies missing assertions, and a recommendation module that suggests improvements. This segmentation allows each module to perform its specific function with high accuracy while keeping the overall system manageable and understandable, reducing the perceived complexity for the designer.
Solution Approach 2:
The system creates a simplified copy of the circuit design in the form of a scheme (graph structure) that captures the essential signal transitions and assertion relationships. This copy can be analyzed automatically with high precision to detect missing assertions, while the original complex circuit design remains unchanged. The copy serves as a tractable representation that enables accurate analysis without requiring direct manipulation of the full design complexity.
3Productivity
If automated assertion verification is implemented, then productivity is improved, but ease of operation decreases due to tool complexity
Solution Approach 1:
The system implements automated feedback by analyzing the circuit design and assertion description, then providing specific recommendations to the designer about missing assertions and coverage gaps. This feedback loop guides the designer through the assertion creation process, automatically identifying issues and suggesting corrections, which improves productivity by reducing manual verification effort while maintaining ease of operation through intuitive guidance rather than requiring the designer to master complex tool operations.
Data Source
AI summary
A program embodied in a non-transitory computer readable medium includes instructions executable by a processor to perform a method of verifying a circuit design. The method includes the steps of performing an automated analysis of the circuit design by scanning an assertion description file and a signal list file of the circuit design, creating and displaying a scheme based on the assertion description file, wherein the scheme includes nodes and arcs, the nodes indicating output signals and the arcs indicating a transition relationship between nodes, and identifying in the scheme assertions that are missing from the assertion description, and recommending amendments to the assertion description to supply the missing assertions, the missing assertions, when added, being reflected in the display of the scheme.