Circuit Editing Structures for FIB Access in IC Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit design, FIB milling processes face challenges in creating high aspect ratio holes due to redeposition of material on side walls, leading to damage of conductive and dielectric layers, especially in dense packing configurations, which can result in shorts or opens and increased dielectric constant in low-density dielectrics.
Innovation Solution
A circuit editing structure comprising multiple patterned metal layers with columns that allow for electrical coupling or decoupling using FIB processing, reducing the need for extensive FIB milling through multiple layers and minimizing damage by limiting changes to upper metal layers, thereby reducing mask redesign costs and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If FIB milling is used to create high aspect ratio holes to access deeply buried conductors, then electrical connections between buried connectors can be established, but material redeposits on side walls causing damage to conductive and dielectric layers
Solution Approach 1:
The patent divides the interconnect structure into multiple metal layers with circuit editing structures positioned in upper layers (e.g., metal layer 5) that provide segmented access points to buried connectors in lower layers. This segmentation allows FIB editing to be performed on upper layers without requiring deep milling through all intermediate layers, thereby reducing material redeposition and damage to sensitive dielectric and conductive layers.
Solution Approach 2:
The patent introduces circuit editing structures that extend vertically through multiple metal layers, creating a new dimensional pathway for accessing buried connectors. Instead of milling horizontally through dense interconnect structures, the vertical circuit editing structures provide direct access routes from upper to lower layers, reducing the need for high aspect ratio horizontal milling and minimizing damage to surrounding layers.
2Reliability
If wide holes are milled to access deeply buried conductors, then electrical connections can be established, but surrounding circuitry in other layers is damaged or exposed resulting in shorts or opens
Solution Approach 1:
The patent applies local quality by creating circuit editing structures with varying widths at different vertical levels. The structures are narrower in upper metal layers where milling is performed and expand toward lower layers, providing localized access exactly where needed. This localized approach ensures reliable electrical connections to buried connectors while minimizing the milling width required and preventing damage to surrounding circuitry in adjacent layers.
3Adaptability or versatility
If FIB milling is performed through multiple layers to reach deeply buried conductors, then connections can be made, but the process becomes increasingly difficult as the number of metal conductive layers increases
Solution Approach 1:
The patent implements preliminary action by pre-forming circuit editing structures during standard photolithography and deposition processes before FIB editing is performed. These structures include openings and conductive paths that are prepared in advance in upper metal layers, so that when FIB editing is needed, the ion beam only needs to mill through a limited number of pre-prepared layers rather than through the entire stack of metal layers, significantly reducing process complexity.
4Reliability
If low-k dielectric materials are used in the interconnect structure, then signal integrity is improved, but the dielectric constant increases significantly during FIB milling due to damage
Solution Approach 1:
The patent extracts or removes the low-k dielectric material from regions where circuit editing structures are formed in upper metal layers. By taking out the dielectric material in these specific regions before FIB editing, the patent eliminates the harmful interaction between the FIB process and the low-k dielectric, preventing dielectric constant increase while maintaining signal integrity in the remaining intact low-k dielectric regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies access to buried layers for modification, reduces damage during FIB processing, lowers production costs, minimizes scrap, and enhances cycle time by limiting changes to upper metal layers, while maintaining the integrity of lower, more sensitive layers.
Implementation Method 1
layers can be sputter-etched by a FIB system to expose underlying layers for observation and testing
Implementation Method 2
to create new connections by the selective deposition of conductive materials
Implementation Method 3
the material sputtered at the bottom of the hole during milling tends to redeposit on the side walls of the hole
Data Source
AI summary
An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.