Circuit Failure Rate Determination via Wire Segment Analysis
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Solution Overview
Problem
Current electromigration (EM) analysis methods are inadequate in guaranteeing EM reliability, leading to pessimistic failure rate overestimations and increased IC design iterations due to insufficient accuracy in predicting circuit failure rates.
Innovation Solution
A method and system for determining failure-in-time (FIT) rates by obtaining circuit data, reliability data, and thermal maps to calculate failure rates for wire segments, identifying disproportionate contributors, and modifying these segments to meet target failure rates, ensuring the circuit is ready for manufacture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If present EM analysis methods are used, then verification steps can be completed, but failure rates are overestimated leading to pessimistic results
Solution Approach 1:
The circuit is divided into multiple clusters, each comprising first and second wire segments. Failure rates are calculated separately for each wire segment within clusters and then aggregated. This segmentation allows for more precise local analysis rather than treating the entire circuit uniformly, thereby improving measurement precision while maintaining reliability verification.
Solution Approach 2:
The patent applies different analysis approaches to different parts of the circuit by identifying clusters with disproportionate contributions to overall failure rates. Wire segments are analyzed individually with their own failure rates calculated based on local characteristics, allowing targeted refinement of accuracy where it matters most without unnecessarily complicating the entire analysis.
2Reliability
If present EM analysis methods are used, then verification can be performed, but the number of IC design iterations increases
Solution Approach 1:
The patent performs preliminary identification of clusters that disproportionately contribute to failure rates before final verification. By calculating failure rates for individual wire segments and identifying problematic clusters in advance, the analysis can focus refinement efforts only where needed, reducing overall iteration time while maintaining reliable EM verification.
Solution Approach 2:
Rather than uniformly analyzing every wire segment with maximum detail, the patent applies refined analysis only to clusters that disproportionately contribute to failure rates. This partial action approach achieves sufficient reliability verification without the excessive time cost of uniform high-detail analysis across the entire circuit.
3Reliability
If wire segments are modified to meet target failure rate, then circuit reliability improves, but design complexity increases
Solution Approach 1:
The patent modifies wire segments locally within identified clusters rather than applying uniform modifications across the entire circuit. By concentrating modifications only in clusters that disproportionately contribute to failure rates, the design achieves improved reliability with minimal added complexity in non-critical areas.
Solution Approach 2:
The circuit is segmented into clusters, allowing independent modification of wire segments within each cluster. This segmentation enables targeted modifications to meet failure rate targets without requiring complex coordinated changes across the entire circuit, thereby reducing overall design complexity while improving reliability.
Data Source
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AI summary
A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.