Circuit Analysis False Path Elimination
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Solution Overview
Problem
Circuit analysis systems often perform analysis on false paths in addition to true paths, leading to inefficiencies and unnecessary processing, as they do not effectively distinguish between the two.
Innovation Solution
A method and system that identify and eliminate false paths in electronic lists associated with circuit units by using a net-identifying module to distinguish between true and false paths, allowing circuit analysis to focus only on true paths through the identification of modified THROUGH nodes and elimination of false-path nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit analysis is performed on all paths in the electronic list, then comprehensive analysis coverage is achieved, but processing time and computational resources are wasted on false paths
Solution Approach 1:
The system performs preliminary identification of false paths using heuristic rules (such as detecting parallel transistors, unbalanced FROM nodes, and modified THROUGH nodes) before the main circuit analysis. This preliminary action filters out false paths in advance, so that the subsequent analysis only processes true paths, thereby maintaining comprehensive analysis coverage while significantly reducing processing time
Solution Approach 2:
The path analysis process is segmented into multiple stages: (1) initial path identification from electronic lists, (2) false path detection using heuristic rules, (3) elimination of identified false paths, and (4) focused analysis on remaining true paths. This segmentation allows the system to handle different types of paths differently, improving overall efficiency
2Reliability
If circuit analysis is performed on all paths in the electronic list, then complete verification is achieved, but computational resources are unnecessarily consumed on false paths
Solution Approach 1:
The system applies preliminary filtering using multiple heuristic rules (parallel transistor detection, unbalanced FROM node detection, modified THROUGH node detection) to identify and eliminate false paths before the main verification process. This ensures that computational resources are only consumed for verifying true paths, maintaining verification completeness while reducing resource consumption
Solution Approach 2:
The system uses the structural information already present in the circuit netlist and path data to automatically identify false paths through self-contained heuristic rules. The false path identification process is self-service in nature, using the circuit's own structural characteristics (transistor connections, node configurations) to reveal false paths without requiring external verification resources
Data Source
AI summary
A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.