Circuit Fault Tree Modeling for Automated Hazard Linkage
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Solution Overview
Problem
The existing methods for creating component fault trees for electric circuits are time-intensive, prone to errors, and require manual adaptation with changes in the circuit, making them inefficient for complex safety-critical systems.
Innovation Solution
An automated method for generating component fault trees using circuit descriptions that include information about components, connections, and fault modes, allowing for the automatic linking of fault modes and modification of links based on hazard trees and circuit information, reducing manual effort and increasing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual methods are used to create component fault trees for electric circuits, then expert knowledge and circuit diagram information can be incorporated, but the process becomes very time-intensive and susceptible to faults
Solution Approach 1:
The patent replaces the manual mechanical process of creating fault trees with an automated computer-based system. The computer automatically generates the component fault tree by processing circuit description data, component fault tree data, and hazard tree data, eliminating manual intervention and reducing time consumption while maintaining reliability through systematic automated processing
Solution Approach 2:
The system enables self-service by allowing the computer to automatically perform the entire fault tree creation process without requiring continuous expert intervention. The automated method processes input data, generates the fault tree structure, and produces results independently, making the process efficient and repeatable
2Adaptability or versatility
If manual fault tree analysis is performed, then comprehensive safety analysis can be achieved, but the process requires repeated manual adaptation when circuits change
Solution Approach 1:
The patent implements dynamics by enabling the fault tree to be automatically updated when circuit changes occur. The computer reads updated circuit description data and regenerates the component fault tree accordingly, making the system adaptive to changes without requiring manual reanalysis, thus improving both adaptability and productivity
Solution Approach 2:
The system incorporates feedback by continuously comparing updated circuit description data with the existing fault tree model. When changes are detected, the computer automatically adjusts the fault tree structure to reflect current circuit conditions, ensuring the analysis remains accurate and up-to-date
3Device complexity
If classic fault trees are used, then traditional fault analysis can be performed, but the structure becomes complex and difficult to manage as system complexity increases
Solution Approach 1:
The patent applies segmentation by breaking down the overall fault tree into component-level fault trees. Each component has its own fault tree that can be independently analyzed and managed. The computer then integrates these component fault trees into a complete system-level fault tree, making the overall complex structure more manageable through modular organization
Solution Approach 2:
The patent introduces a new dimension by organizing fault trees hierarchically from component level to system level. This multi-level structure allows analysis to proceed from individual components upward, adding a dimensional organization that simplifies management of complex systems while maintaining comprehensive coverage
Data Source
AI summary
Various embodiments include modeling a component fault tree for a circuit with an input-side and an output-side component. These include using a fault tree corresponding to a hazard for each respective component, obtaining information about the components of the circuit and a connection between components, and connecting the respective fault trees based on the circuit description. Each fault tree includes an input fault mode or a basic event and an output fault mode. The output fault mode and the input fault mode are each assigned to a component terminal. An output fault mode of the input-side component tree is connected to an input fault mode of the output-side component tree if: there is a connection between the assigned terminal of the input-side component and the output-side component and the output fault mode of the input-side component correlates to an input fault mode of the output-side component.


