Circuit Design Frequency Optimization via Path Segmentation
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Solution Overview
Problem
Circuit design operating frequency is limited by loop paths, and pipelining feed-forward paths to meet target frequency can adversely affect design correctness, necessitating a method to optimize placement and routing while relaxing timing constraints.
Innovation Solution
Distinguish between loop and feed-forward paths in a circuit design, relax timing constraints of feed-forward paths to prioritize loop paths during placement and routing, and optionally insert pipeline stages into feed-forward paths to increase operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelining is applied to increase operating frequency, then the operating frequency is improved, but the correctness of the circuit design deteriorates
Solution Approach 1:
The patent segments the circuit design into two distinct types of paths: loop paths and feed-forward paths. This segmentation allows different timing constraint strategies to be applied to each path type. Loop paths maintain strict timing constraints to ensure correctness, while feed-forward paths can have relaxed constraints that enable frequency improvement through pipelining without compromising overall design correctness.
Solution Approach 2:
The patent applies local quality by imposing different timing constraint characteristics on different parts of the circuit. Specifically, loop paths are given high-priority timing constraints that must be met to ensure correctness, while feed-forward paths are given relaxed timing constraints that allow for frequency optimization. This localized differentiation resolves the contradiction by allowing pipelining in appropriate regions without affecting critical regions.
2Speed
If timing constraints are relaxed to allow higher operating frequency, then the operating frequency is improved, but the placement and routing optimization deteriorates
Solution Approach 1:
The patent segments timing constraints into path-specific constraints rather than applying a uniform constraint across the entire circuit. By identifying and separately constraining loop paths versus feed-forward paths, the system can optimize placement and routing for loop paths with strict constraints while allowing feed-forward paths to benefit from relaxed constraints that enable higher frequency operation.
Solution Approach 2:
The patent dynamically changes timing constraint parameters based on path type. Loop paths maintain original strict timing constraints to ensure placement and routing optimization, while feed-forward paths have their timing constraints relaxed (parameter changed) to allow for higher operating frequencies. This selective parameter modification resolves the contradiction between frequency improvement and optimization quality.
3Device complexity
If uniform timing constraints are applied to all paths, then the placement and routing is simplified, but the operating frequency is limited by the slowest path
Solution Approach 1:
The patent divides the circuit's timing constraints into separate categories based on path type (loop vs. feed-forward). This segmentation allows the system to manage complexity through structured classification while enabling higher frequencies by not being constrained by the slowest single path. The segmented approach balances complexity management with frequency optimization.
Solution Approach 2:
The patent applies partial action by relaxing timing constraints only for feed-forward paths while maintaining strict constraints for loop paths. This selective relaxation allows the circuit to operate at higher frequencies determined by loop paths rather than being limited by feed-forward path delays, achieving frequency improvement without requiring complete redesign of all timing constraints.
Data Source
AI summary
Processing a circuit design includes determining that an operating frequency for a first placement and routing for the circuit design does not exceed a target operating frequency, distinguishing between loop paths and feed-forward paths in the circuit design, and, responsive to determining that the operating frequency does not exceed the target operating frequency, relaxing timing constraints of the feed-forward paths using a processor. A second placement and routing is performed on the loop paths and the feed-forward paths of the circuit design.


