Circuit Graph k4 Structure Reduction for Layer Assignment
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Solution Overview
Problem
The existing methods for assigning nodes in circuit design to layers during lithography face challenges such as layer conflicts and high computational complexity, especially when dealing with large circuit designs, as they often result in inefficient use of resources and prolonged processing times due to the NP-complete nature of the colorability problem.
Innovation Solution
The proposed method involves reducing the graph size by removing k4 structures, which are structures with four interconnected nodes, and then assigning layers to the reduced graph, followed by reassigning layers to the removed nodes using specific rules to minimize conflicts, thereby reducing the computational load and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If graph reduction by removing k4 structures is applied, then processing time is reduced, but layer assignment accuracy may deteriorate
Solution Approach 1:
The circuit design graph is segmented into k4 structures (complete subgraphs of 4 nodes) that are identified and removed separately from the main graph. This segmentation allows the layer assignment problem to be solved on a smaller reduced graph first, then the removed k4 structures are reintegrated and assigned layers based on their connections to the reduced graph, thereby reducing overall processing time while maintaining accuracy.
Solution Approach 2:
The layer assignment is performed preliminarily on the reduced graph (after removing k4 structures) before dealing with the complete graph. This preliminary action establishes a base layer assignment for the majority of nodes, which then serves as a foundation for assigning layers to the removed k4 structure nodes, reducing the computational complexity of the overall problem.
2Device complexity
If graph reduction is applied to minimize nodes and connections, then computational complexity is reduced, but the completeness of layer assignment may worsen
Solution Approach 1:
The k4 structures are extracted (taken out) from the main circuit design graph to form a separate set of removed nodes. This extraction reduces the computational complexity of the layer assignment problem by working with a smaller reduced graph. The extracted k4 structures are then reintegrated in a second phase where their layer assignments are determined based on their connection relationships with nodes in the reduced graph, ensuring complete and reliable layer assignment for all original nodes.
Solution Approach 2:
The reduced graph serves as an intermediary structure that mediates between the original complete graph and the final layer assignment. By first performing layer assignment on the reduced graph and then using those results to guide the layer assignment of the removed k4 structures, the method ensures that the completeness and reliability of the final layer assignment is maintained while benefiting from reduced computational complexity.
3Use of energy by moving object
If k4 structures are removed and reassigning is performed, then resource usage is optimized, but the number of steps increases
Solution Approach 1:
The layer assignment is performed in a preliminary phase on the reduced graph before reintegrating the removed k4 structures. This preliminary action optimizes resource usage by concentrating computational efforts on the smaller reduced graph first, using fewer processor and memory resources. The second phase of reassigning layers to removed nodes uses the preliminary results as a foundation, reducing the overall resource requirements despite the additional step.
Solution Approach 2:
The k4 structures are taken out (extracted) from the main graph to create a reduced graph that requires fewer computational resources for processing. This extraction separates the problem into two manageable phases: first assigning layers to the reduced graph with optimized resource usage, then assigning layers to the extracted nodes using the established assignments as references, thereby optimizing overall resource consumption.
Data Source
AI summary
The present disclosure describes systems and methods for assigning nodes in a circuit design to layers. The method includes identifying a plurality of structures in a circuit design. Each of the plurality of structures includes four nodes of the circuit design and each of the four nodes are connected to every other node in the respective structure. The method also includes removing, from the plurality of structures, an even number of pairs of connected nodes of the circuit design to form a reduced node structure and assigning circuit layers for the nodes in the reduced node structure. The method further includes assigning, by a processing device, circuit layers for the pairs of connected nodes removed from the plurality of structures based on the assigned circuit layers for the nodes in the reduced node structure.