Circuit Graph Partitioning for Parallel Simulation
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Solution Overview
Problem
Current circuit simulation methods are inefficient in handling complex integrated circuits due to the need to consider parasitic effects, leading to increased computational complexity and time, especially in nanometer, gigahertz, low power VLSI design, where power and signal integrity are critical.
Innovation Solution
The method employs system or network tearing to partition a circuit into subtrees, allowing for distributed, parallel computing to solve each subtree independently, with results combined to obtain real solutions for the entire circuit, thereby speeding up simulation and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuit simulation includes parasitic effects and large system matrices, then accuracy is improved, but computation time and complexity increase significantly
Solution Approach 1:
The circuit network is partitioned into multiple subtrees using graph theory, where each subtree represents a manageable subcircuit. This segmentation allows the large system matrix to be divided into smaller submatrices that can be processed independently and in parallel, maintaining accuracy while reducing computational time and complexity.
2Measurement precision
If circuit simulation includes parasitic effects and large system matrices, then accuracy is improved, but device complexity increases
Solution Approach 1:
The complex circuit network is segmented into multiple independent subtrees, transforming a single large complex system into several smaller, more manageable subsystems. Each subtree can be analyzed with simpler computational methods, reducing overall computational complexity while maintaining simulation accuracy through the inclusion of parasitic effects.
3Productivity
If distributed parallel computing is used to solve subtrees, then productivity is improved, but device complexity increases
Solution Approach 1:
The circuit is divided into independent subtrees that can be solved simultaneously using distributed parallel computing. This segmentation enables productivity improvement through parallel processing while managing system complexity by organizing the computation into structured, independent tasks that can be coordinated through a systematic interface.
Data Source
AI summary
A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.