Circuit Hard Error Simulation Using Reference Execution Trace
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Solution Overview
Problem
Current design simulation methods are inefficient in determining a circuit's susceptibility to hard errors and simulating functionality under such errors, as they require naively simulating each fault independently, which is time-consuming and resource-intensive.
Innovation Solution
The method involves computing hard-error test coverage by utilizing a recording of a reference execution to speed up simulation processes, focusing on nodes that are potentially affected by errors and using monitoring signals to identify critical and undetectable nodes, thereby reducing computational requirements and optimizing simulation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional independent fault simulation is used to determine circuit susceptibility to hard errors, then comprehensive error coverage is achieved, but simulation time and computational resources increase significantly
Solution Approach 1:
The patent performs a preliminary reference simulation to capture the good execution trace before conducting fault simulations. This pre-computed trace is then reused across multiple fault simulations, eliminating the need to re-simulate unaffected circuit portions and significantly reducing total simulation time while maintaining comprehensive error coverage
Solution Approach 2:
The patent merges multiple fault simulations by using a single reference execution trace that serves as the basis for all fault simulations. Instead of running separate complete simulations for each fault, the method combines them by reusing the reference trace and only simulating the affected portions, thereby reducing overall computational effort
2Measurement precision
If complete circuit simulation is performed for each fault to ensure accurate coverage measurement, then precise test coverage determination is achieved, but computational complexity and resource requirements increase
Solution Approach 1:
The patent segments the circuit simulation into two parts: a reference simulation that captures the good execution trace, and fault-specific simulations that only need to simulate the portions of the circuit affected by each fault. This segmentation allows accurate coverage measurement by focusing computational resources only on relevant circuit portions while maintaining overall coverage accuracy
Data Source
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AI summary
A method, apparatus and product for hard error simulation and usage thereof. The method comprises obtaining a design of a circuit, which comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a trace of a run of a test of the circuit; and obtaining a hard error fault on a node. The method comprises determining a hard-error test coverage for the hard error fault, wherein the hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the hard error fault during an execution of the test, and wherein said determining comprises: simulating the execution of the circuit together with the hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault. An indication of the hard-error test coverage may be outputted.