Circuit Location Identifier Layer for Faster Defect Mapping
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Solution Overview
Problem
Existing electronic apparatus face challenges in efficiently locating defective circuits, particularly in memory devices, due to repetitive and complex circuit connections, which can lead to errors in identification and remediation.
Innovation Solution
The implementation of a location identifier layer with a repetitive pattern, such as a metal mesh, that includes section labels like symbols, letters, and numbers, allows for easier identification and location of circuit components and defects by providing visual references.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional counting methods using circuit connections are used to locate defective circuits, then circuit defects can be identified, but the process becomes repetitive, time-consuming, and error-prone due to the large number of memory cells and repetitive circuit connections
Solution Approach 1:
The patent divides the memory device into multiple sections with unique identifiers. Instead of counting individual circuit connections across the entire device, the location identifier layer segments the device into manageable sections that can be independently identified and located, dramatically reducing the time and complexity of defect location.
Solution Approach 2:
The patent introduces a location identifier layer as an intermediary between the circuit layer and the defect location process. This layer contains unique identifiers for each section, serving as a mediator that simplifies the defect location process by providing direct visual references instead of requiring complex circuit connection counting.
2Ease of operation
If circuit connections are used as reference marks for locating defects, then defect positions can be determined, but the repetitive and numerous connections increase the difficulty and error rate of identification
Solution Approach 1:
The patent extracts the location identification function from the circuit connections themselves and places it in a separate location identifier layer. This separation removes the complexity of circuit connections from the identification process, allowing defects to be located using simple visual references to unique identifiers rather than complex circuit tracing.
Solution Approach 2:
The patent creates a simplified copy of location information in the location identifier layer that mirrors the physical layout of the device. This copy contains unique identifiers for each section, providing an easy-to-use reference system that replicates the device structure without the complexity of actual circuit connections.
3Difficulty of detecting and measuring
If visual inspection is performed on the top metal layer to locate defects, then surface defects can be detected, but the repetitive mesh pattern of the metal layer makes it difficult to reference and identify specific defect locations
Solution Approach 1:
The patent applies local quality by making each section of the location identifier layer unique with distinct identifiers, while the surrounding metal mesh maintains its repetitive pattern. This allows visual inspection to easily identify specific locations by their unique identifiers without being confused by the repetitive metal pattern, as each section has a distinctive visual signature.
Data Source
AI summary
An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.