Circuit Label Relabeling for Subcircuit Recognition
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Solution Overview
Problem
Current methods for finding subcircuits in larger circuits are inefficient and inaccurate, as they do not generalize to different subcircuit structures and fail to provide sufficient information for precise identification.
Innovation Solution
The method involves unidirectional relabeling of vertices in both the subcircuit and the larger circuit, allowing for deeper recursion and ensuring that labels include enough information about the circuit topology, enabling accurate identification of subcircuit instances through recursive relabeling and circuit tracing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ad hoc techniques are used for finding subcircuits, then the process can be performed with simple implementation, but the method does not generalize to different subcircuit structures and lacks accuracy
Solution Approach 1:
The patent changes the parameter of label information by recursively updating labels to include topology information from neighboring vertices. This transformation enables the labels to capture structural characteristics of subcircuits, allowing the method to generalize across different subcircuit structures while maintaining high identification accuracy through comprehensive topological information.
2Adaptability or versatility
If the SubGemini relabeling method is used, then technology independence is achieved, but the labels do not include sufficient information for accurate identification under certain circumstances
Solution Approach 1:
The patent adds a new dimension to the labeling process by incorporating information from neighboring vertices into each label. This dimensional expansion transforms the labels from simple vertex identifiers to comprehensive topological descriptors that capture the structural context, thereby preventing information loss while maintaining technology independence.
Solution Approach 2:
The patent implements a nested information structure where labels contain not only vertex information but also embedded topology information from neighboring vertices. This nesting allows each label to encapsulate multiple levels of structural detail, ensuring sufficient information is retained for accurate subcircuit identification while preserving the technology-independent framework.
3Measurement precision
If deeper recursion of relabeling is performed, then labels include sufficient topology information for accurate identification, but the computational complexity and time increase
Solution Approach 1:
The patent performs preliminary relabeling operations to populate labels with topology information before the actual subcircuit matching process. This preliminary action ensures that when matching occurs, the labels already contain sufficient topological context, eliminating the need for repeated or deeper recursion during the matching phase and thereby reducing overall computation time while maintaining high accuracy.
Data Source
AI summary
A method for identifying instances of a smaller circuit in a larger circuit is provided. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. The method includes recursively relabeling of each of the plurality of vertices until labels of all neighboring vertices of a selected vertex are zero. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Each successive iteration of the relabeling uses labels of each of the plurality of vertices after a previous iteration of the relabeling. Then, a recursive circuit tracing operation is performed.