Circuit Layout Design for Semiconductor Annealing Uniformity
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Solution Overview
Problem
The non-uniform distribution of semiconductor structures across a wafer during rapid thermal annealing leads to temperature and electric performance variations, as dummy structures cannot be added to certain regions like under inductors or MIM capacitors without affecting circuit performance.
Innovation Solution
A design method for circuit layout that establishes relationships between device electric parameters, annealing temperature, and STI patterns to adjust gate pattern lengths, avoiding the need for dummy structures by using STI patterns to reflect AA and Poly-Si densities and compensate for non-uniformities in STI patterns distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If dummy structures are added to balance reflectivity during RTA, then temperature uniformity is improved, but electric performance of circuits in sensitive regions deteriorates
Solution Approach 1:
The patent applies local quality by adjusting gate pattern lengths specifically in particular regions (such as under inductors or MIM capacitors) rather than uniformly across the entire wafer. This allows temperature compensation in sensitive regions without adding dummy structures that would degrade circuit performance, while maintaining appropriate reflectivity characteristics in non-sensitive regions.
Solution Approach 2:
The patent changes the parameter of gate pattern length in particular regions to compensate for temperature non-uniformity. By modifying the gate length parameter locally, the method achieves temperature balance during RTA without introducing dummy structures, thereby avoiding negative impacts on electric performance in sensitive circuit regions.
2Temperature
If gate pattern length is adjusted in particular regions, then temperature uniformity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by adjusting gate pattern lengths during the circuit layout design stage before manufacturing. This advance adjustment incorporates temperature compensation directly into the mask design, eliminating the need for additional dummy structure fabrication steps and reducing overall manufacturing complexity despite the customized gate lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves temperature uniformity and electric parameter consistency across the wafer without adding dummy structures, maintaining the integrity of sensitive circuit regions.
Implementation Method 1
rapid thermal annealing method for semiconductor apparatus
Implementation Method 2
establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns
Data Source
AI summary
The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures.