Circuit Layout Generation via Consolidated Netlist for LDE Precision
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Solution Overview
Problem
The scaling down of integrated circuit (IC) geometry increases the significance of layout-dependent effects (LDEs), which are typically evaluated with insufficient precision after circuit layout generation, impacting device characteristics like carrier mobility and threshold voltage.
Innovation Solution
A method is introduced that generates layout geometry parameters to reduce the gap between pre-layout and post-layout simulations by converting an original netlist into a consolidated netlist, incorporating LDE-related instance parameters, and performing pre- and post-layout simulations to iteratively refine the circuit layout, ensuring accurate consideration of LDEs during the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If circuit layout is generated and LDE parameters are extracted based on the layout, then LDE evaluation precision is improved, but design iteration time increases
Solution Approach 1:
The patent applies preliminary action by performing pre-layout simulation that incorporates LDE considerations before the actual layout is generated. The system predicts LDE impacts using the netlist and design rules, allowing designers to address LDE issues early in the design process rather than waiting for post-layout extraction, thus reducing iteration time while maintaining precision
Solution Approach 2:
The patent creates a virtual model of the circuit layout through pre-layout simulation, copying the essential geometric and electrical characteristics needed to evaluate LDEs without requiring the actual physical layout to be drawn first. This virtual representation allows LDE analysis to proceed in parallel with layout development
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency is improved, but LDE significance increases
Solution Approach 1:
The patent applies preliminary anti-action by predicting and compensating for LDE effects before they manifest in the actual scaled-down circuit. The pre-layout simulation identifies potential LDE problems caused by small geometry dimensions and allows corrective actions to be taken in the design stage, counteracting the harmful effects before they impact production
Solution Approach 2:
The patent changes the parameters used in simulation by incorporating LDE-related instance parameters into the netlist, transforming the simulation approach to account for layout-dependent effects. This parameter enhancement allows the simulation to reflect the actual behavior of scaled-down geometries, enabling designers to optimize layouts to minimize LDE impacts while maintaining high functional density
3Measurement precision
If pre-layout simulation incorporates LDE parameters, then simulation accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies partial action by selectively applying LDE considerations to only those circuit elements and layout regions where LDE effects are most significant. Rather than performing exhaustive LDE analysis on every component, the system focuses computational resources on critical areas, achieving high simulation accuracy for the most important LDE impacts without the full computational burden of complete analysis
Data Source
AI summary
A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.