Circuit Layout Verification via DC Voltage Analysis
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Solution Overview
Problem
Existing circuit layout verification methods are inefficient, requiring significant computational resources and time, and often rely on human judgment due to limitations in simulating voltage relationships between layout traces.
Innovation Solution
A circuit layout verification method and system that perform a direct current (DC) analysis on a circuit layout by setting preset parameters for components, calculating maximum and minimum voltage values for wire segments, and marking segments as abnormal if they exceed predetermined design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SPICE simulation is used to verify circuit layout electrical characteristics, then verification accuracy is improved, but verification time and computational resources increase significantly
Solution Approach 1:
The patent segments the verification process into two distinct stages: (1) topology verification using SPICE simulation to check electrical characteristics and connectivity, and (2) geometry verification using a dedicated layout verification system to check trace routing, spacing, and physical constraints. This segmentation allows each verification type to be performed with appropriate tools and methods, reducing overall verification time while maintaining accuracy.
Solution Approach 2:
The patent introduces an intermediate data exchange mechanism between the SPICE simulation results and the layout verification system. The topology verification results serve as input constraints for the geometry verification, allowing the system to focus computational resources on critical areas and reduce redundant calculations during layout verification.
2Reliability
If comprehensive circuit layout verification is performed to detect all design issues, then manufacturing yield is improved, but computational resources and complexity increase
Solution Approach 1:
The verification system is segmented into multiple independent modules: topology verification module, geometry verification module, constraint checking module, and reporting module. Each module handles specific verification tasks, reducing the complexity of any single component while collectively achieving comprehensive verification to improve manufacturing yield.
Solution Approach 2:
The system implements feedback mechanisms where verification results from one stage inform subsequent verification stages. Failed checks trigger targeted re-verification or design modifications, allowing the system to focus computational resources on critical issues rather than performing exhaustive verification on all elements, thus managing complexity while maintaining high reliability.
3Manufacturing precision
If detailed electrical characteristic verification is performed on circuit geometry, then design quality is improved, but the verification process becomes infeasible without manual judgment
Solution Approach 1:
The patent introduces an automated interpretation layer that acts as an intermediary between raw verification data and design decisions. The system automatically interprets verification results, identifies critical issues, and generates actionable recommendations, eliminating the need for manual judgment while maintaining high design quality through detailed electrical characteristic verification.
Solution Approach 2:
The verification system performs self-service by automatically detecting, analyzing, and reporting design issues without requiring manual intervention. The system independently evaluates electrical characteristics against design constraints, identifies violations, and provides detailed reports, making the complex verification process as easy to operate as simply launching the verification tool.
Data Source
AI summary
A method for circuit layout verification in a computing device includes: reading a circuit layout; setting parameters for components in the circuit layout; according to a preset voltage value of at least one port in the circuit layout, performing DC analysis on the circuit layout after the setting is performed to calculate a maximum possible voltage value and a minimum possible voltage value of a wire segment on the circuit layout; and inputting the maximum possible voltage value and the minimum possible voltage value into a predetermined design specification, wherein when the maximum possible voltage value or minimum possible voltage value exceeds the predetermined design specification, the wire segment is marked as abnormal.