Circuit Layout Graph Reduction for Multi-Patterning Conflict Checking
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Solution Overview
Problem
In semiconductor fabrication, existing multi-patterning technologies face challenges in efficiently checking and optimizing circuit layouts for compatibility with fewer photomasks, leading to increased complexity and potential redesigns due to spacing conflicts between conductive lines.
Innovation Solution
A method involving graph representation and reduction techniques, such as K4-1 reduction and square loop reduction, is applied to circuit layouts to identify and resolve conflicts, allowing for compatibility checks with fewer photomasks and reducing processing time by iteratively applying these methods until the layout is compatible with triple or quadruple patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple patterning methods are used to achieve smaller spacings, then layout flexibility and IC density are improved, but process complexity and checking difficulty increase
Solution Approach 1:
The patent segments the complex multi-patterning checking problem into distinct phases: graph generation from layout, graph reduction through systematic rules (K4-1 reduction, square loop reduction, degree-4 node reduction), and conflict detection. This segmentation transforms an intractable overall checking problem into manageable sequential steps, reducing computational complexity while maintaining layout density benefits.
Solution Approach 2:
The patent applies preliminary graph reduction operations before performing the actual conflict checking. By pre-processing the graph through reduction rules that eliminate redundant nodes and edges, the system prepares a simplified representation that makes subsequent checking more efficient, thereby reducing overall process complexity.
2Loss of time
If graph reduction methods are applied to check compatibility with fewer photomasks, then processing time is reduced, but checking accuracy may be compromised
Solution Approach 1:
The patent implements a feedback mechanism where graph reduction is followed by conflict checking, and if conflicts are detected or the graph cannot be reduced further, the system provides feedback to indicate layout incompatibility. This feedback loop ensures that reductions do not compromise accuracy, as the reduced graph is specifically designed to preserve conflict detection capability while reducing processing time.
Solution Approach 2:
The patent creates a simplified copy of the original layout in the form of a graph representation, where complex geometric details are abstracted into nodes and edges. This copying approach maintains the essential topological relationships needed for conflict detection while eliminating unnecessary complexity, thereby reducing processing time without sacrificing checking accuracy.
3Device complexity
If K4-1 reduction and square loop reduction are iteratively applied, then graph complexity is reduced, but computational overhead increases
Solution Approach 1:
The patent applies reduction rules in periodic iterations rather than continuously. Each iteration applies a specific reduction rule (K4-1, square loop, or degree-4 node reduction) until no further reductions are possible, then moves to the next rule set. This periodic application reduces computational overhead by avoiding redundant processing while systematically reducing graph complexity through multiple passes.
Data Source
AI summary
A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.