Circuit Layout Placement With Node Flipping for Shorter Routing
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Solution Overview
Problem
Existing layout placement and routing methods often result in mismatched input/output connections, leading to increased tracks, longer routing lengths, and inconsistent current directions, which negatively affect chip design quality.
Innovation Solution
A method for layout placement and routing that involves generating layout units along a preset direction, defining assessment nodes, and determining position flips based on positional relationships to optimize the placement of layout units, ensuring consistent node distribution and reduced routing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If automatic layout placement or manual placement is used, then layout units can be placed in the layout, but the input/output order of connection nodes does not match the device direction, leading to increased tracks and longer routing lengths
Solution Approach 1:
The patent applies preliminary action by performing position flip determination on layout units before routing is executed. The system calculates position information of assessment nodes and determines whether to flip layout units in advance, ensuring that connection nodes are properly oriented before the routing process begins. This prevents mismatched input/output orders and reduces routing length from the outset.
Solution Approach 2:
The patent applies inversion by flipping layout units upside down or sideways when the position information indicates that connection nodes are in an incorrect orientation. This principle directly addresses the mismatch between connection node order and device direction by inverting the layout unit's orientation, thereby aligning input/output nodes with the correct device direction and reducing the need for additional tracks and routing length.
2Productivity
If traditional placement methods are used, then layout units can be arranged, but current direction becomes inconsistent, negatively affecting chip design quality
Solution Approach 1:
The patent applies feedback by continuously monitoring the position information of assessment nodes and the orientation of connection nodes during layout placement. The system uses this feedback to determine whether each layout unit needs to be flipped, ensuring that current direction remains consistent across all layout units. This feedback mechanism maintains stable current direction composition throughout the chip design, improving overall design quality.
Data Source
AI summary
Embodiments relate to the field of semiconductors, and provide a method for layout placement and routing, a circuit layout, an electronic device, and a storage medium. The method includes: generating a plurality of layout units (100) arranged along a preset direction (X) based on a schematic circuit diagram, each of the plurality of layout units (100) having a plurality of connection nodes (101), and two connection nodes (101) at two ends of each of the plurality of layout units (100) being defined as assessment nodes; determining any one of the plurality of layout units (100) as a target layout unit, and obtaining a positional relationship between the connection nodes (101) in rest of the plurality of layout units having same node information as the assessment nodes in the target layout unit and the assessment nodes; and performing routing to electrically connect the connection nodes (101) having the same node information.