Circuit Layout Segmentation for Double Patterning Fidelity
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Solution Overview
Problem
Conventional photolithography technologies face challenges in forming fine patterns with minimal spacings and dimensions due to pattern development anomalies, particularly in negative tone development, when the total area of feature patterns exceeds the development barrier and the width or area ratios of connected segments are significantly different.
Innovation Solution
A method is introduced to decompose the original layout into two layouts, identify and cut selected segments with a cutting pattern to ensure the width and area ratios of the separated portions do not exceed the development barrier, using double patterning technology with two photomasks to form the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to form fine patterns with minimal spacings, then manufacturing capability is maintained, but pattern development anomalies occur when feature pattern area exceeds development barrier
Solution Approach 1:
The patent segments a feature pattern with large total area into multiple disconnected sub-patterns by inserting cutting patterns. This segmentation reduces the effective area of each sub-pattern below the development barrier, preventing development anomalies while maintaining the overall pattern geometry and dimensions
Solution Approach 2:
The cutting pattern acts as an intermediary element that is inserted into the feature pattern to divide it into separate portions. This intermediary structure enables the large-area pattern to be processed as multiple small-area patterns, avoiding development issues while preserving the original design intent
2Manufacturing precision
If double patterning technology is used to manufacture fine patterns with small critical dimensions, then existing exposure equipment can be utilized, but pattern development anomalies still occur in negative tone development
Solution Approach 1:
The patent applies segmentation by dividing the feature pattern into multiple sub-patterns through cutting patterns. This ensures that each sub-pattern has sufficient spacing and area ratio within acceptable ranges, preventing development anomalies during negative tone development while maintaining fine pattern dimensions
Solution Approach 2:
The patent modifies the geometric parameters of the pattern by controlling the spacing and area ratios of connected segments. By adjusting these parameters to fall within acceptable ranges, the patent prevents development anomalies while maintaining the required critical dimensions for fine patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces pattern development anomalies by ensuring well-defined pattern formation, allowing for the creation of fine patterns with consistent dimensions and spacings using existing exposure equipment.
Implementation Method 1
Photolithography is one of the most critical processes in IC fabrication, which usually involves exposure and development steps to transfer the designed layout patterns such as patterns of implant/non-implant regions or circuit structures, for example, on a photomask to a photoresist layer on the substrate
Implementation Method 2
The patterned photoresist layer is then utilized as a mask for an ion implantation or etching process, thereby transferring the designed layout patterns to the substrate
Implementation Method 3
The patterned photoresist layer is then utilized as a mask for an ion implantation or etching process, thereby transferring the designed layout patterns to the substrate
Data Source
AI summary
A method for forming a circuit structure includes decomposing an original layout into a first layout and a second layout, identifying a first pattern-to-cut in the first layout, selecting a first selected segment among the segments of the first pattern-to-cut, and inserting a first cut pattern to the first selected segment. The method further includes, after the first pattern-to-cut subtracting the first cut pattern, outputting the first layout to a first photomask and the second layout and the first cut pattern to a second photomask, and using the first photomask and the second photomask to perform a double patterning process to form the circuit structure on a substrate.