Circuit Layout Reserved Space Optimization for Dynamic IR Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for determining circuit layout do not adequately consider toggle rate, leading to inefficient placement of decoupling capacitors, resulting in increased IR drop and degraded circuit performance, and higher costs.
Innovation Solution
A method using simulation software to determine the size of reserved space for decoupling capacitors based on toggle rate, optimizing circuit layout by sorting blocks according to toggle rates and adjusting reserved space to minimize dynamic IR drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reserved space for DCAP is determined by random or experience-based methods, then the design process is simple, but the dynamic IR drop cannot be effectively reduced
Solution Approach 1:
The patent changes the parameter from fixed or random reserved space to dynamic reserved space that varies according to toggle rate. The reserved space is calculated based on the formula: reserved space = base space + (toggle rate × coefficient), where high toggle rate areas receive larger reserved spaces for DCAP placement, directly addressing the dynamic IR drop problem through parameter optimization
Solution Approach 2:
The patent performs preliminary analysis of toggle rates during the design phase before final layout completion. By pre-calculating which areas have high toggle rates and pre-reserving appropriate spaces for DCAP in those areas, the system proactively prevents dynamic IR drop issues rather than addressing them after they occur
2Reliability
If more space is reserved for DCAP in high toggle rate areas, then dynamic IR drop is reduced, but space utilization decreases
Solution Approach 1:
The patent applies local quality by making the reserved space non-uniform across different areas. Instead of reserving equal space everywhere, the system reserves larger spaces specifically in high toggle rate areas (such as near CPU, GPU, DDR memory) and smaller or no reserved spaces in low toggle rate areas, optimizing both IR drop reduction and space utilization through localized adaptation
Solution Approach 2:
The patent uses partial action by applying DCAP reservation selectively only where needed (high toggle rate areas) rather than uniformly across the entire board. This partial application of the reservation strategy reduces unnecessary space consumption in low-toggle-rate areas while maintaining sufficient protection in critical areas
3Reliability
If reserved space is increased in areas with high component placement density, then dynamic IR drop is reduced, but component placement flexibility decreases
Solution Approach 1:
The patent performs preliminary identification of high toggle rate areas using simulation software analysis before final component placement. By determining which areas require DCAP reservation in advance, the system can plan component placement around these reserved spaces, maintaining flexibility in low-toggle-rate areas while ensuring protection in critical high-density areas
Data Source
AI summary
A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).