Circuit Design Layout and SEM Image Registration via Gaussian Filtering
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Solution Overview
Problem
Current methods for registering circuit design layouts and scanning electron microscope images lack efficiency and accuracy, particularly in complex lithography processes where optical proximity correction is necessary to mitigate imaging errors.
Innovation Solution
A method involving binarization and Gaussian filtering of images to align circuit design layouts with scanning electron microscope images using image template matching, ensuring accurate registration by maximizing gray values at central axes of design and scanning patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional registration methods are used to align circuit design layouts with SEM images, then registration can be performed, but the process is slow and lacks efficiency
Solution Approach 1:
The patent segments the complex registration process into distinct stages: image preprocessing (binarization, Gaussian filtering), feature extraction (identifying central axes of patterns), and alignment computation. This segmentation allows each stage to be optimized independently, significantly improving registration speed while maintaining accuracy.
Solution Approach 2:
The patent applies preliminary actions by performing binarization and Gaussian filtering on both the circuit design layout and SEM images before the actual registration process. These preprocessing steps prepare the data in advance, making the subsequent alignment computation faster and more efficient.
2Measurement precision
If conventional registration methods are used, then alignment can be achieved, but measurement precision and registration accuracy are insufficient
Solution Approach 1:
The patent applies local quality by focusing computational resources on critical regions - specifically the central axes of patterns where measurement precision is most important. By identifying and aligning these key features rather than processing entire images uniformly, the method achieves high registration accuracy while managing complexity.
Solution Approach 2:
The patent changes parameters through systematic preprocessing: converting images to binary form (0 and 1 values) and applying Gaussian filtering with specific standard deviations. These parameter transformations enhance the prominence of central axes and patterns, enabling more accurate measurement and registration.
3Manufacturing precision
If detailed binarization and filtering processes are applied to maximize gray values at central axes, then registration accuracy improves, but computational complexity increases
Solution Approach 1:
The patent extracts the essential information needed for registration by taking out only the central axes and key pattern features from the complete images. Through binarization and Gaussian filtering, it isolates the critical geometric information while discarding redundant data, achieving high precision without excessive computational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a quick and accurate registration method for circuit design layouts and scanning electron microscope images, enhancing the precision of error calculations and improving imaging quality in semiconductor manufacturing.
Implementation Method 1
Gaussian filtering the binary image of the circuit design layout and the binary image of the scanning electron microscope image to make the gray value to be the largest at central axes of areas where the design pattern and the scanning pattern are located
Data Source
AI summary
The present invention provides a method for registering a circuit design layout and a scanning electron microscope image. The method comprises: step S1, providing a circuit design layout and a scanning electron microscope image; step S2: processing the circuit design layout to acquire a binary design layout image, and processing the scanning electron microscope image to acquire a binary scanning electron microscope image; step S3: performing Gaussian filtering on the binary design layout image and the binary scanning electron microscope image to maximize a gray value at a central axis of regions corresponding to a design pattern and a scanned pattern; and Step S4: performing registration according to the central axis of the design pattern and the scanned pattern. The present invention also provides a system for registering a circuit design layout and a scanning electron microscope image, a circuit design layout and an imaging error calculation method thereof, and an electronic device. The method and system for registering a circuit design layout and a scanning electron microscope image, the circuit design layout and the imaging error calculation method thereof, and the electronic device feature accurate registration and accurate error calculation.