Circuit Optimization Using Linear Delay Models and Progressive Evaluation
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Solution Overview
Problem
Circuit optimization techniques face performance bottlenecks due to computationally expensive timing updates, which are often exponential with respect to the circuit design's size, making them inefficient during logic and physical synthesis.
Innovation Solution
The approach involves dynamically pruning the library of gates, using a linear delay model for evaluation, sorting gates and input pins based on criteria for early rejection, and performing progressive evaluation to reduce computation and improve optimization efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full timing update is performed for entire circuit during gate replacement, then timing accuracy is improved, but computational complexity increases exponentially
Solution Approach 1:
The patent segments the circuit into a local region around the gate being optimized and the rest of the circuit. Only the local region undergoes timing update when a gate is replaced, while the rest of the circuit reuses previously computed timing information. This segmentation reduces computational complexity from exponential (full circuit) to polynomial (local region only), while maintaining timing accuracy through selective updates.
Solution Approach 2:
The patent performs preliminary timing analysis on the entire circuit before the optimization loop begins. This preliminary action computes timing information that can be reused during subsequent gate replacements, avoiding the need to perform full timing updates for every replacement operation. The preliminary action establishes a foundation that reduces computational burden during iterative optimization.
2Measurement precision
If full timing update is performed for entire circuit during gate replacement, then timing information accuracy is improved, but runtime performance deteriorates
Solution Approach 1:
The timing update operation is segmented to affect only the local region surrounding the optimized gate rather than the entire circuit. This segmentation maintains timing information accuracy for the affected region while dramatically improving runtime performance by avoiding redundant updates to unaffected circuit portions.
Solution Approach 2:
The patent applies partial action by performing timing updates only where necessary (local region) rather than excessively updating the entire circuit. This partial approach maintains sufficient timing accuracy for optimization decisions while improving runtime performance through reduced computational workload.
3Manufacturing precision
If large library of gates is considered for optimization, then optimization quality is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary filtering of the gate library before the main optimization process. Gates are pre-evaluated and sorted based on their potential to improve circuit metrics, and only the most promising gates are retained for detailed evaluation. This preliminary action maintains optimization quality by preserving high-potential gates while reducing processing time through elimination of clearly inferior options.
Solution Approach 2:
The patent applies partial action by considering only a subset of the full gate library during optimization iterations. Instead of exhaustively evaluating every gate in the library, the method selectively processes gates that are most likely to yield improvements, thereby maintaining optimization quality while significantly reducing processing time.
Data Source
AI summary
Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.