Circuit Logic for Multi-Clock Data Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data coherency issues arise in electronic devices operating with multiple clock domains, such as those using Joint Test Action Group (JTAG) technology, where significant differences in clock speeds lead to inconsistencies.
Innovation Solution
A system and method that utilize circuit logic to receive and manage multiple clock signals, resetting the logic between data operations to maintain coherency, ensuring that data is accurately obtained and provided to testing logic using both Test Clock (TCK) and Functional Clock (FCK).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock signals with substantially different speeds are used in the system, then the system can operate in different clock domains (increasing versatility), but data coherency problems result (decreasing reliability)
Solution Approach 1:
The system performs a reset operation on the storage circuitry before obtaining each datum to ensure data coherency. This preliminary action clears any potential coherency issues that might arise from operating across multiple clock domains with substantially different speeds, allowing the system to reliably retrieve data regardless of clock domain differences.
2Adaptability or versatility
If data is obtained and output using multiple clock signals with different speeds, then the system can interface with different clock domains (increasing adaptability), but data coherency cannot be maintained without resetting (decreasing reliability)
Solution Approach 1:
The system periodically resets the storage circuitry between obtaining different data items. This periodic reset action ensures that data coherency is maintained across multiple clock domains, allowing the system to interface with different clock domains while reliably maintaining data integrity through repeated coherency restoration.
3Reliability
If the storage logic is reset before each data operation, then data coherency is maintained (improving reliability), but additional reset operations increase processing time (decreasing productivity)
Solution Approach 1:
The system extracts and applies the reset operation specifically to the storage circuitry portion that may contain incoherent data, rather than resetting the entire system. This targeted approach maintains data coherency in the critical storage elements while minimizing the impact on overall processing speed and productivity.
Data Source
AI summary
A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.