Parallel Circuit Simulation Matrix Partitioning via Hypergraph Segmentation
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Solution Overview
Problem
Circuit simulators face significant challenges in performing scalable parallel matrix solving, particularly during transient analysis of full-chip mixed-signal designs, where the matrix solver often becomes a bottleneck due to the difficulty in achieving efficient parallel processing.
Innovation Solution
The system employs a hypergraph partitioner to convert the matrix representation into a bordered block diagonal (BBD) matrix, which is then reordered to facilitate parallel processing by associating diagonal submatrices with processors and solving them independently, along with an interconnect submatrix after the diagonal submatrices are solved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional matrix solving methods are used in circuit simulators, then the matrix solver can handle general circuit equations, but the solver becomes a bottleneck during transient analysis due to difficulty in achieving efficient parallel processing
Solution Approach 1:
The circuit matrix is segmented into multiple independent submatrices through partitioning techniques. Each submatrix can be solved independently by different processors, enabling parallel computation. This segmentation transforms a single large matrix solving problem into multiple smaller, concurrently solvable subproblems, directly addressing the bottleneck in transient analysis.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing the matrix solution across multiple processors in a distributed architecture. Instead of sequentially solving the entire matrix on a single processor, the solution space is expanded to utilize spatial distribution of computational tasks across multiple processing units, achieving scalable parallel performance.
2Loss of time
If the matrix solver is optimized for parallel processing, then transient analysis can be completed faster, but the complexity of achieving scalable parallel matrix solving increases
Solution Approach 1:
The matrix is divided into partitioned submatrices that can be independently processed. This segmentation enables straightforward parallel implementation where each processor handles specific submatrices, reducing the time required for transient analysis while maintaining manageable complexity through modular organization.
Solution Approach 2:
The matrix is pre-processed and partitioned into suitable submatrices before the actual solving process begins. This preliminary organization of the matrix structure facilitates efficient parallel processing by pre-establishing the division of labor among processors, thereby reducing simulation time without introducing complex runtime coordination mechanisms.
3Productivity
If conventional sequential matrix solving is used, then implementation is simpler, but transient runs take days or weeks to complete for full-chip mixed-signal designs
Solution Approach 1:
The large circuit matrix is segmented into multiple smaller submatrices that can be solved simultaneously. This segmentation enables the simulation throughput to increase linearly with the number of processors, reducing transient analysis duration from days or weeks to much shorter periods while maintaining implementation feasibility through modular processing.
Solution Approach 2:
The patent transitions from sequential single-processor solving to parallel multi-processor solving by adding the dimension of temporal concurrency. Multiple matrix solutions are executed simultaneously across different processors, dramatically increasing circuit simulation throughput and reducing the time required for transient analysis of full-chip designs.
Data Source
AI summary
Over the years, parallel processing has become increasingly common. Conventional circuit simulators have not taken full advantage of these developments, however. Here, a circuit simulator and system are provided that partitions circuit matrices to allow for more efficient parallel processing to take place. By doing this, the overall speed and reliability of the circuit simulator can be increased.