Circuit Modeling via Net List Simplification for Noise Simulation
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Solution Overview
Problem
As semiconductor devices become more miniaturized and integrated, the simulation execution time for identifying noise effects from power distribution networks (PDNs) increases, making it difficult to assess the impact of noises on semiconductor device operations.
Innovation Solution
A circuit modeling system that includes a processor and storage device, which identifies active and inactive semiconductor devices, reduces the power distribution network (PDN) by removing unnecessary nodes and forming compressive lines, and generates a simplified net list for simulation, thereby reducing simulation execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation is performed using the complete circuit layout with all semiconductor devices, then the accuracy of noise effect identification is improved, but the simulation execution time increases drastically
Solution Approach 1:
The circuit layout is segmented into multiple sub-layouts based on operational states. The semiconductor devices are divided into first semiconductor devices (active state) and second semiconductor devices (inactive state), creating separate simulation scenarios that can be processed independently and more efficiently
Solution Approach 2:
The inactive second semiconductor devices are extracted and removed from the simulation model. By taking out only the necessary first semiconductor devices that are currently active, the simulation focuses on relevant circuit portions, reducing execution time while maintaining noise effect accuracy for active devices
Solution Approach 3:
The simulation approach is made dynamic by switching between different operational states. The system dynamically identifies which semiconductor devices are active versus inactive and adjusts the simulation model accordingly, allowing efficient time-staged analysis of noise effects across different operating conditions
2Loss of time
If the power distribution network is reduced by removing nodes and forming compressive lines, then the simulation execution time is reduced, but the accuracy of noise impact assessment may be compromised
Solution Approach 1:
Multiple PDN nodes are merged into compressive lines that represent aggregated electrical characteristics. The compressive lines combine the electrical properties (resistance, capacitance) of multiple original nodes into equivalent simplified representations, reducing node count while preserving noise impact accuracy
Solution Approach 2:
The PDN parameters are transformed from individual node values to aggregated compressive line parameters. By changing the representation from discrete nodes to equivalent compressive lines with consolidated electrical parameters, the model becomes simpler while maintaining electrical behavior accuracy for noise analysis
Data Source
AI summary
A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.