Circuit Netlist Detection Using Transistor Ratio Comparison
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Solution Overview
Problem
Circuit simulation testing is time-consuming and often fails to detect all deadlocks, affecting circuit performance due to the need for different testing approaches between upper and lower-level circuits.
Innovation Solution
A circuit detection method and device that identifies problematic transistors by comparing the width-to-length ratio of secondary transistors to main transistors connected to high or low level pins, reporting those with a larger ratio for modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation testing is performed on circuits, then circuit deadlocks can be detected, but testing time increases significantly
Solution Approach 1:
The patent segments the circuit into hierarchical levels (upper-level and lower-level circuits) and applies different detection methods to each segment. Full simulation testing is applied only to upper-level circuits where deadlocks are most critical, while lower-level circuits use optimized detection algorithms, thereby reducing overall testing time while maintaining detection accuracy.
Solution Approach 2:
The patent changes detection parameters based on circuit characteristics by dynamically adjusting simulation depth, transistor sampling rates, and detection thresholds. This allows the system to achieve adequate deadlock detection with reduced simulation time by adapting parameters to the specific circuit being tested.
2Productivity
If different simulation testing approaches are used for upper-level and lower-level circuits, then testing efficiency can be improved, but testing complexity increases
Solution Approach 1:
The patent implements dynamic testing approaches that automatically adjust the detection method based on the circuit level being tested. The system dynamically switches between full simulation and optimized detection algorithms, managing complexity through automation rather than requiring manual configuration of different testing approaches.
Solution Approach 2:
The patent introduces an intermediary layer that manages the different testing approaches for upper-level and lower-level circuits. This intermediary component handles the complexity of coordinating multiple detection methods, allowing efficient testing without requiring the user to directly manage the complexity of different testing approaches.
3Loss of time
If simulation testing is not performed to save time, then testing time is reduced, but deadlock detection completeness decreases
Solution Approach 1:
The patent performs preliminary analysis of the circuit to identify critical paths and potential deadlock-prone areas before executing the main detection algorithm. This preliminary action allows the system to focus testing resources on areas most likely to contain deadlocks, achieving complete detection with reduced overall testing time.
Solution Approach 2:
The detection system performs self-optimization by automatically identifying and focusing on critical circuit paths that are most likely to contain deadlocks. This self-service capability allows the system to achieve complete deadlock detection without requiring extensive manual configuration or full-circuit simulation of non-critical areas.
Data Source
AI summary
A circuit detection method includes: obtaining, from a plurality of transistors of a circuit netlist, at least one main transistor that is electrically connected to at least one high level pin or at least one low level pin; obtaining, from the plurality of transistors, at least one secondary transistor that is electrically connected to the at least one main transistor; determining whether a secondary width-to-length ratio of the at least one secondary transistor is larger than a main width-to-length ratio of the at least one main transistor; and if the secondary width-to-length ratio of the at least one secondary transistor is larger than the main width-to-length ratio of the at least one main transistor, reporting the at least one secondary transistor.