Automated Circuit Noise Parameter Extraction via Parasitic Capacitance
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Solution Overview
Problem
Manual analysis of parasitic capacitance between signal lines in integrated circuits is time-consuming and labor-intensive, especially after layout revisions, leading to inefficiencies in development and analysis due to the large number of signal lines and complex operating state combinations.
Innovation Solution
A method that automatically determines parasitic capacitance and logic states of signal lines across various operating states, calculating noise parameters by combining the logic states and parasitic capacitance to streamline the process and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual analysis is used to determine parasitic capacitance and noise parameters of signal lines, then measurement precision can be maintained, but productivity is significantly reduced due to time-consuming operations
Solution Approach 1:
The patent replaces manual mechanical analysis operations with automated computer-based calculation systems. The system automatically determines parasitic capacitance values and noise parameters through computational methods, eliminating the need for manual analysis while maintaining measurement precision through systematic calculation approaches.
Solution Approach 2:
The patent enables the analysis system to automatically perform all necessary calculations and determinations without human intervention. The computer system self-services by automatically determining parasitic capacitance, calculating noise parameters, and generating analysis results, thereby significantly improving productivity while maintaining precision through consistent automated processes.
2Measurement precision
If manual analysis is performed for each layout revision, then analysis accuracy can be maintained, but loss of time increases significantly due to repeated remaking of all analyses
Solution Approach 1:
The patent establishes a systematic framework that pre-defines the analysis methodology and computational approaches. By setting up the analysis system in advance with predefined parameters and calculation methods, the system can quickly adapt to layout revisions without requiring complete remaking of analyses, thus reducing time loss while maintaining accuracy.
Solution Approach 2:
The patent creates a dynamic analysis system that can efficiently adapt to changes in circuit layouts. The automated computational approach allows the system to dynamically recalculate only the affected portions when layouts are revised, rather than requiring complete reanalysis, thereby maintaining accuracy while minimizing time loss.
3Reliability
If comprehensive analysis of all operating states is performed manually, then reliability of noise parameter determination is improved, but device complexity increases due to the number of operating state combinations
Solution Approach 1:
The patent segments the complex analysis task into manageable computational steps. The system divides the determination of noise parameters across multiple operating states into discrete calculation stages, handling each state combination systematically through automated computation, thereby maintaining reliability without overwhelming complexity.
Solution Approach 2:
The patent creates a universal analysis system that handles multiple operating states and circuit configurations through a single automated framework. The computational system performs various analysis functions (parasitic capacitance determination, noise parameter calculation, logic state analysis) through unified algorithms, reducing the perceived complexity while maintaining comprehensive reliability.
Data Source
AI summary
A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.