Circuit Obfuscation via Encrypted Look-Up Tables
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Solution Overview
Problem
Existing methods for protecting circuit designs in Application Specific ICs (ASICs) and Field Programmable Gate Arrays (FPGAs) are vulnerable to attacks such as piracy, reverse engineering, and hardware Trojan insertion, with current obfuscation techniques like Netlist Logic Locking and Satisfiability Attack Resistant logic Locking being susceptible to key-pruning attacks.
Innovation Solution
The method involves analyzing a combinational circuit to identify logic gates implementable by look-up tables, dividing it into encrypted and non-encrypted portions, storing the encrypted portion in memory, and interfacing the remaining logic gates to generate outputs using decrypted information upon enablement, with the decrypted information being removed upon trigger events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic locking obfuscation methods (NLL, SARLock, SLL) are used to protect circuit designs, then reverse engineering resistance is improved, but the circuits become vulnerable to key-pruning attacks
Solution Approach 1:
The circuit is divided into multiple segments: original logic gates, inserted key-gates, and additional logic gates. The key-gates are strategically placed to control signal flow, and the additional logic gates are used to mask the original circuit functionality. This segmentation makes key-pruning attacks ineffective because removing key-gates would disrupt the carefully balanced logic structure.
Solution Approach 2:
Key-gates act as intermediaries between input signals and the original logic circuit. These key-gates control whether the original circuit functionality is revealed or masked. The additional logic gates serve as intermediaries that obfuscate the relationship between inputs and outputs, making it difficult for attackers to determine the correct key values through analysis.
2Reliability
If additional logic gates (key-gates) are inserted into the gate level netlist to lock circuit functionality, then protection against unauthorized access is improved, but device complexity increases
Solution Approach 1:
The key-gates are merged with the original logic gates in the netlist, and the additional logic gates are integrated into the existing circuit structure. This merging approach allows the obfuscation logic to share resources and pathways with the original circuit, minimizing the increase in overall complexity while maintaining strong protection.
Solution Approach 2:
The additional logic gates serve multiple functions: they mask the original circuit functionality, provide additional layers of obfuscation, and work in conjunction with key-gates to control signal flow. This multi-functionality reduces the need for separate dedicated protection circuits, thereby limiting the complexity increase.
3Reliability
If logic locking is applied to obfuscate circuit functionality until a secret key is loaded, then intellectual property protection is improved, but the circuit produces incorrect outputs in the nonfunctional state which may indicate vulnerability
Solution Approach 1:
The obfuscation is applied locally at specific points in the circuit where key-gates control critical signal paths. The additional logic gates are strategically placed to mask functionality in the most sensitive areas. This localized approach ensures that incorrect outputs in the nonfunctional state are confined to specific regions, making vulnerability detection more difficult while maintaining overall protection effectiveness.
Data Source
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AI summary
Systems and methods for protecting intellectual property of a circuit via obfuscation of logic through encryption. The methods comprise: analyzing a combinational circuit (CC) to identify first logic gates that perform first function(s) which is(are) implementable by LUT(s); dividing CC a first portion comprising the first logic gates and a second portion comprising remaining logic gates; protecting gate logic of the first portion by at least storing information implementing the first function(s) in an encrypted LUT format in a memory device of the circuit such that the first function(s) is(are) obfuscated when the circuit is in an at-rest state; and interfacing the remaining logic gates with the memory device such that the circuit is configured to generate an output in accordance with operations of the combinational circuit using the information stored in the encrypted LUT format.