Circuit Design Obfuscation via Multi-Table Mapping
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Solution Overview
Problem
Circuit designs implemented on programmable integrated circuits (ICs) are vulnerable to reverse engineering, allowing unauthorized access and copying due to the complexity of designs and the ability to retrieve and analyze configuration bitstreams.
Innovation Solution
The method involves mapping circuit designs to hardware components using multiple tables, introducing atypical logic patterns and sub-circuits subject to race conditions, and obfuscating configuration data to mislead automated inference tools and require manual inspection, while ensuring correct operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If configuration data is made easily accessible for automated retrieval and analysis, then ease of operation is improved, but security against reverse engineering deteriorates
Solution Approach 1:
The patent introduces an intermediary analysis process that manually inspects configuration data through a series of analysis stages. This intermediary layer prevents direct automated access to the actual circuit logic, as the configuration data must pass through multiple verification steps and semantic analysis layers before any meaningful reverse engineering can occur. The intermediary process transforms easily accessible data into a form that resists automated parsing while maintaining human interpretability.
Solution Approach 2:
The patent segments the configuration data into multiple analysis stages and components. Instead of presenting a monolithic configuration bitstream, the data is divided into configuration records, signal assignments, instance definitions, and connectivity information that must be processed sequentially through multiple analysis stages. This segmentation prevents automated tools from extracting complete circuit logic in a single operation, as each segment must be individually verified and cross-referenced.
2Difficulty of detecting and measuring
If multiple mapping tables and atypical logic patterns are introduced, then difficulty of detecting and measuring is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by transforming standard logic patterns into atypical implementations. Configuration data is encoded using non-standard mapping relationships between hardware components and logic functions. Instead of using conventional LUT mappings, the system employs custom-defined mapping tables that associate hardware components with unconventional logic patterns. This parameter transformation makes automated inference tools ineffective, as they expect standard logic mappings rather than the customized patterns used in the configuration data.
Solution Approach 2:
The patent introduces asymmetry by using non-standard, irregular mapping relationships in the configuration data. The mapping tables employ asymmetric associations between hardware components and logic functions that do not follow conventional symmetric patterns. For example, hardware components are mapped to logic patterns that are intentionally non-intuitive and non-standard. This asymmetric encoding makes it difficult for automated inference tools to predict or reverse-engineer the circuit logic, as the patterns deliberately deviate from expected symmetric logic implementations.
3Object-affected harmful factors
If configuration data is obfuscated with inconsistent circuits, then security against reverse engineering is improved, but reliability of operation deteriorates
Solution Approach 1:
The patent applies preliminary action by introducing a verification stage that executes before the actual circuit operation. The system performs preliminary semantic analysis and consistency checking of the configuration data to ensure correctness before the circuit is deployed. This preliminary verification action identifies and corrects potential obfuscation errors or inconsistencies, ensuring that the circuit will operate reliably once deployed. The preliminary action prevents faulty or inconsistent configuration data from reaching the operational stage.
Solution Approach 2:
The patent implements feedback mechanisms that continuously monitor and verify circuit operation against the original design specifications. The system includes verification logic that compares actual circuit behavior during operation against expected behavior defined in the configuration data. If inconsistencies or errors are detected, the feedback mechanism triggers alerts or automatic corrections. This feedback loop ensures that any obfuscation or inconsistency in the configuration data is detected and resolved, maintaining reliable operation while preserving security.
Data Source
AI summary
Various methods for inhibiting reverse engineering of a circuit design are provided. In one embodiment, a circuit design is initially mapped to a plurality of identified hardware components of a target device using a first table that indicates a first set of logic patterns that hardware components of the target device can implement. Unused hardware components are identified, and at least one logic pattern of the circuit design is remapped to one of the unused hardware components using a second mapping table. The second table indicates a second set of logic patterns, not indicated by the first mapping table, that one of the unused hardware components is configurable to implement.