Circuit Partitioning for Balanced Independent Simulation Jobs
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Solution Overview
Problem
Simulating large circuits is computationally intensive and memory-intensive, leading to long simulation times and potential memory bottlenecks, especially when reconstructing waveforms.
Innovation Solution
The method involves partitioning a large circuit into balanced subgraphs by removing startpoint vertices, computing small and large weakly connected components, and using greedy algorithms to cluster these components into balanced subgraphs that can be simulated independently with an upper-bounded memory footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large circuit is simulated using a single simulator, then simulation accuracy is maintained, but simulation time increases and memory requirements exceed available capacity
Solution Approach 1:
The circuit is partitioned into multiple balanced subgraphs by removing startpoint vertices and computing weakly connected components. Each subgraph can be simulated independently, enabling parallel processing that reduces simulation time while maintaining accuracy through comprehensive coverage of all circuit behaviors
Solution Approach 2:
The simulation problem is transformed from a single sequential simulation to multiple parallel simulations by adding the dimension of parallel processing. Independent simulation jobs are distributed across multiple processors or machines, converting a time-consuming sequential task into a parallel endeavor that reduces overall simulation time
2Reliability
If a large circuit is simulated using a single simulator, then complete circuit behavior is captured, but memory footprint exceeds available memory
Solution Approach 1:
The circuit is divided into multiple smaller subgraphs that fit within available memory constraints. Each subgraph is simulated independently, allowing the memory footprint to be bounded by the size of individual subgraphs rather than the entire circuit, thus enabling simulation on machines with limited memory resources
Solution Approach 2:
Multiple independent simulation jobs are performed on different subgraphs, with each job using only the memory required for its specific subgraph. This partial action approach allows the total simulation to be completed using distributed memory resources across multiple machines, exceeding what a single machine could provide
3Productivity
If the circuit is partitioned into multiple subgraphs for parallel simulation, then simulation time is reduced, but job distribution complexity increases
Solution Approach 1:
The circuit is pre-partitioned into balanced subgraphs with controlled sizes before simulation begins. This preliminary partitioning ensures that subsequent job distribution is straightforward, as each subgraph can be independently assigned to available simulation resources without complex coordination requirements during the actual simulation phase
4Adaptability or versatility
If startpoint vertices are removed to create weakly connected components, then independent simulation jobs are enabled, but graph structure complexity increases
Solution Approach 1:
Removing startpoint vertices naturally segments the circuit graph into weakly connected components, creating independent simulation jobs. This segmentation approach simplifies the overall simulation system by enabling independent processing of each component, despite the increased complexity in graph representation
Data Source
AI summary
Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.